489 research outputs found
Design and development of deadline based scheduling mechanisms for multiprocessor systems
Multiprocessor systems are nowadays de facto standard for both personal
computers and server workstations. Benefits of multicore technology will be
used in the next few years for embedded devices and cellular phones as well.
Linux, as a General Purpose Operating System (GPOS), must support many
different hardware platform, from workstations to mobile devices. Unfortu-
nately, Linux has not been designed to be a Real-Time Operating System
(RTOS). As a consequence, time-sensitive (e.g. audio/video players) or sim-
ply real-time interactive applications, may suffer degradations in their QoS.
In this thesis we extend the implementation of the “Earliest Deadline First”
algorithm in the Linux kernel from single processor to multicore systems,
allowing processes migration among the CPUs. We also discuss the design
choices and present the experimental results that show the potential of our
work
Toward an Undergraduate MIS Curriculum Model for Caribbean Institutions
Colleges and universities in the United States with undergraduate programs offer undergraduate Management Information Systems programs in their business schools to complement and balance computer science and computer engineering curricula. Similar institutions in the English-speaking Caribbean, however, slant their computing studies overwhelmingly toward Computer Science , which produces technologists for the IT industry. Although the vast majority of their graduates are engaged in applying technology solutions to information problems in business organizations, these English-speaking Caribbean institutions offer limited MIS programs, which prepare graduates for such roles. This article examines undergraduate computing curricula in the Caribbean and compares them with others elsewhere in the world. It recommends that English-speaking Caribbean universities give similar prominence to MIS education in their business programs in order to equip graduates to create more effective IT-enabled business solutions
On-Chip Optical Interconnection Networks for Multi/Manycore Architectures
The rapid development of multi/manycore technologies offers the opportunity for highly parallel architectures implemented on a single chip. While the first, low-parallelism multicore products have been based on simple interconnection structures (single bus, very simple crossbar), the emerging highly parallel architectures will require complex, limited-degree interconnection networks. This thesis studies this trend according to the general theory of interconnection structures for parallel machines, and investigates some solutions in terms of performance, cost, fault-tolerance, and run-time support to shared-memory and/or message passing programming mechanisms
Cost models for structured parallel programming on shared memory architectures
Shared memory architectures are widely taking place. Following the structured parallel programming approach, a cost model is fundamental for performance portability and predictability. This thesis gives a contribution about cost models for multiprocessors and multi-cores taking into account important characteristics of new generation shared memory architectures, e.g. hierarchical shared memory, and with particular focus on the impact of the parallel application
Discrete Event Simulations
Considered by many authors as a technique for modelling stochastic, dynamic and discretely evolving systems, this technique has gained widespread acceptance among the practitioners who want to represent and improve complex systems. Since DES is a technique applied in incredibly different areas, this book reflects many different points of view about DES, thus, all authors describe how it is understood and applied within their context of work, providing an extensive understanding of what DES is. It can be said that the name of the book itself reflects the plurality that these points of view represent. The book embraces a number of topics covering theory, methods and applications to a wide range of sectors and problem areas that have been categorised into five groups. As well as the previously explained variety of points of view concerning DES, there is one additional thing to remark about this book: its richness when talking about actual data or actual data based analysis. When most academic areas are lacking application cases, roughly the half part of the chapters included in this book deal with actual problems or at least are based on actual data. Thus, the editor firmly believes that this book will be interesting for both beginners and practitioners in the area of DES
Structured Parallel Programming and Cache Coherence in Multicore Architectures
It is clear that multicore processors have become the building blocks of today’s high-performance computing platforms. The advent of massively parallel single-chip microprocessors further emphasizes the gap that exists between parallel architectures and parallel programming maturity. Our research group, starting from the experiences on distributed and shared memory multiprocessor, was one of the first to propose a Structured Parallel Programming approach to bridge this gap. In this scenario, one of the biggest problems is that an application’s performance is often affected by the sharing pattern of data and its impact on Cache Coherence. Currently multicore platforms rely on hardware or automatic cache coherence techniques that allow programmers to develop programs without taking into account the problem. It is well known that standard coherency protocols are inefficient for certain data communication patterns and these inefficiencies will be amplified by the increased core number and the complex memory hierarchies.
Following a structured parallelism approach, our methodology to attack these problems is based on two interrelated issues: structured parallelism paradigms and cost models (or performance models).
Evaluating the performance of a program, although widely studied, is still an open problem in the research community and, notably, specific cost models to de- scribe multicores are missing. For this reason in this thesis, we define an abstract model for cache coherent architectures, which is able to capture the essential elements and the qualitative behaviors of multicore-based systems. Furthermore, we show how this abstract model combined with well known performance modelling techniques, such as analytical modelling (e.g., queueing models and stochastic process algebras) or simulations, provide an application- and architecture-dependent cost model to predict structured parallel applications performances.
Starting out from the behavior and performance predictability of structured parallelism schemes, in this thesis we address the issue of cache coherence in multicore architectures, following an algorithm-dependent approach, a particular kind of software cache coherence solution characterized by explicit cache management strategies, which are specific of the algorithm to be executed. Notably, we ensure parallel correctness by exploiting architecture-specific mechanisms and by defining proper data structures in order to “emulate” cache coherence solutions in an efficient way for each computation. Algorithm-dependent cache coherence can be efficiently implemented at the support level of structured parallelism paradigms, with absolute transparency with respect to the application programmer. Moreover, by using the cost model, in this thesis we study and compare different algorithm-dependent implementations, such as those based on automatic cache coherence with respect to an original, non-automatic and lock-free solution based on interprocessor communications. Notably, with this latter implementation, in some cases, we are able to reduce the number of memory accesses, cache transfers and synchronizations and increasing computation parallelism with respect to the use of automatic cache coherence.
Current architectures do not usually allow disabling automatic cache coherence. However, the emergence of many-core architectures somewhat changed the scenario, so that some architectures, such as the Tilera TilePro64, allow to control and disable the automatic cache coherence facilities. For this reason, in this thesis we finally apply our methodology to TilePro64 platform in order provide a further validation of the results obtained by our cost model
- …