Physics and Modeling of Submicron Devices. Annual Report: August I, 1987 - July 31, 1988

The work described in this report is directed at understanding quantum transport phenomena in sub-micron heterostructure devices, at developing computational techniques for modeling such devices, and at applying these techniques to develop new device concepts. During the past year we have (l) applied a previously developed collisionless quantum device model (SEQUAL) and Monte Carlo model (DEMON) to the design and study of heterojunction bipolar transistors (Chapter 2); (2) developed a technique for the analysis of arbitrarily shaped quantum devices with elastic scattering (Chapter 3); and (3) developed an approach for incorporating inelastic dissipative processes in quantum transport theory (Chapter 4). As a by-product of the research, several heterostructure device models have been developed: 1- and 2-D equilibrium models, 1- and 2-D drift-diffusion models, a I-D Monte Carlo simulator and a 1-D collisionless quantum device model. These simulation programs are being applied to advanced device analysis at a number of laboratories and are available to SRC members on reques

Diamond power devices: State of the art, modelling and figures of merit

With its remarkable electro-thermal properties such as the highest known thermal conductivity (~22W/cmbold dotK at room temperature) of any material, high hole mobility (> 2000cm2/Vbold dots), high critical electric field (>10MV/cm), and large bandgap (5.47eV), diamond has overwhelming advantages over silicon and other wide bandgap semiconductors (WBG) for ultra-high- voltage and high temperature applications (>3kV and >450 K, respectively). However, despite their tremendous potential, fabricated devices based on this material have not delivered yet the expected high-performance. The main reason behind this is the absence of shallow donor and acceptor species. The second reason is the lack of consistent physical models and design approaches specific to diamond-based devices that could significantly accelerate their development. The third reason is that the best performances of diamond devices are expected only when the highest electric field in reverse bias can be achieved, something that has not been widely obtained yet. In this context, high temperature operation and unique device structures based on the 2DHG formation represent two alternatives which could alleviate the issue of the incomplete ionization of dopant species. Nevertheless, ultra-high temperature operations and device parallelization could result in severe thermal management issues and affect the overall stability and long-term reliability. Additionally, problems connected to the reproducibility and the long-term stability of 2DHG based-devices still need to be resolved. This review paper aims at addressing these issues by providing the power device research community with a detailed set of physical models, device designs and challenges associated to all the aspects of the diamond power device value chain, from the definition of figures of merits, the material growth and processing conditions, to packaging solutions and targeted applications. Finally, the paper will conclude with suggestions on how to design power converters with diamond devices and will provide the roadmap of diamond devices development for power electronics.This work was supported by the U.K. Engineering and Physical Sciences Research Council for the University of Cambridge Centre for Doctoral Training under Grant EP/M506485/1 and by the French ANR Research Agency under grant ANR-16-CE05-0023 #Diamond-HVDC. The research leading to these results has been performed within the GREENDIAMOND project and received funding from the European Community's Horizon 2020 Programme (H2020/2014–2020) under grant agreement no. 640947

2 GHz +14 dBm CMOS power amplifier for Low Power Wide Area Networks

Abstract. The design of a radiofrequency power amplifier (RF PA) for narrowband low-power wide area networks is presented in this thesis. Particularly, this RF PA is compliant with the 3GPP TS 36.101 standard for a NB1 device within the Power Class 6. To minimize silicon area consumption, this CMOS RF PA employs a single-ended single-stage topology, avoiding inter-stage matching network inductors and output baluns. This RF PA produces +14 dBm of output power with a PAE of 25% and an EVM better than 4% (−28 dB). Also, its out-of-band and spurious emissions satisfy the standard specifications with a large margin. Furthermore, it provides high ruggedness, tolerating an antenna mismatch with a VSWR of 8:1

Spintronics: Fundamentals and applications

Spintronics, or spin electronics, involves the study of active control and manipulation of spin degrees of freedom in solid-state systems. This article reviews the current status of this subject, including both recent advances and well-established results. The primary focus is on the basic physical principles underlying the generation of carrier spin polarization, spin dynamics, and spin-polarized transport in semiconductors and metals. Spin transport differs from charge transport in that spin is a nonconserved quantity in solids due to spin-orbit and hyperfine coupling. The authors discuss in detail spin decoherence mechanisms in metals and semiconductors. Various theories of spin injection and spin-polarized transport are applied to hybrid structures relevant to spin-based devices and fundamental studies of materials properties. Experimental work is reviewed with the emphasis on projected applications, in which external electric and magnetic fields and illumination by light will be used to control spin and charge dynamics to create new functionalities not feasible or ineffective with conventional electronics.Comment: invited review, 36 figures, 900+ references; minor stylistic changes from the published versio

Electrical overstress and electrostatic discharge failure in silicon MOS devices

This thesis presents an experimental and theoretical investigation of electrical failure in MOS structures, with a particular emphasis on short-pulse and ESD failure. It begins with an extensive survey of MOS technology, its failure mechanisms and protection schemes. A program of experimental research on MOS breakdown is then reported, the results of which are used to develop a model of breakdown across a wide spectrum of time scales. This model, in which bulk-oxide electron trapping/emission plays a major role, prohibits the direct use of causal theory over short time-scales, invalidating earlier theories on the subject. The work is extended to ESD stress of both polarities. Negative polarity ESD breakdownis found to be primarily oxide-voltage activated, with no significant dependence on temperature of luminosity. Positive polarity breakdown depends on the rate of surface inversion, dictated by the Si avalanche threshold and/or the generation speed of light-induced carriers. An analytical model, based upon the above theory is developed to predict ESD breakdown over a wide range of conditions. The thesis ends with an experimental and theoretical investigation of the effects of ESD breakdown on device and circuit performance. Breakdown sites are modelled as resistive paths in the oxide, and their distorting effects upon transistor performance are studied. The degradation of a damaged transistor under working stress is observed, giving a deeper insight into the latent hazards of ESD damage

csi and csi7 current source inverters for modular transformerless pv inverters

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