119 research outputs found

    Study Of Nanoscale Cmos Device And Circuit Reliability

    Get PDF
    The development of semiconductor technology has led to the significant scaling of the transistor dimensions -The transistor gate length drops down to tens of nanometers and the gate oxide thickness to 1 nm. In the future several years, the deep submicron devices will dominate the semiconductor industry for the high transistor density and the corresponding performance enhancement. For these devices, the reliability issues are the first concern for the commercialization. The major reliability issues caused by voltage and/or temperature stress are gate oxide breakdown (BD), hot carrier effects (HCs), and negative bias temperature instability (NBTI). They become even more important for the nanoscale CMOS devices, because of the high electrical field due to the small device size and high temperature due to the high transistor densities and high-speed performances. This dissertation focuses on the study of voltage and temperature stress-induced reliability issues in nanoscale CMOS devices and circuits. The physical mechanisms for BD, HCs, and NBTI have been presented. A practical and accurate equivalent circuit model for nanoscale devices was employed to simulate the RF performance degradation in circuit level. The parameter measurement and model extraction have been addressed. Furthermore, a methodology was developed to predict the HC, TDDB, and NBTI effects on the RF circuits with the nanoscale CMOS. It provides guidance for the reliability considerations of the RF circuit design. The BD, HC, and NBTI effects on digital gates and RF building blocks with the nanoscale devices low noise amplifier, oscillator, mixer, and power amplifier, have been investigated systematically. The contributions of this dissertation include: It provides a thorough study of the reliability issues caused by voltage and/or temperature stresses on nanoscale devices from device level to circuit level; The more real voltage stress case high frequency (900 MHz) dynamic stress, has been first explored and compared with the traditional DC stress; A simple and practical analytical method to predict RF performance degradation due to voltage stress in the nanoscale devices and RF circuits was given based on the normalized parameter degradations in device models. It provides a quick way for the designers to evaluate the performance degradations; Measurement and model extraction technologies, special for the nanoscale MOSFETs with ultra-thin, ultra-leaky gate oxide, were addressed and employed for the model establishments; Using the present existing computer-aided design tools (Cadence, Agilent ADS) with the developed models for performance degradation evaluation due to voltage or/and temperature stress by simulations provides a potential way that industry could use to save tens of millions of dollars annually in testing costs. The world now stands at the threshold of the age of nanotechnology, and scientists and engineers have been exploring here for years. The reliability is the first challenge for the commercialization of the nanoscale CMOS devices, which will be further downscaling into several tens or ten nanometers. The reliability is no longer the post-design evaluation, but the pre-design consideration. The successful and fruitful results of this dissertation, from device level to circuit level, provide not only an insight on how the voltage and/or temperature stress effects on the performances, but also methods and guidance for the designers to achieve more reliable circuits with nanoscale MOSFETs in the future

    Boundary layer flow and heat transfer over a permeable shrinking sheet with partial slip

    Get PDF
    The steady, laminar flow of an incompressible viscous fluid over a shrinking permeable sheet is investigated. The governing partial differential equations are transformed into ordinary differential equations using similarity transformation, before being solved numerically by the shooting method. The features of the flow and heat transfer characteristics for different values of the slip parameter and Prandtl number are analyzed and discussed. The results indicate that both the skin friction coefficient and the heat transfer rate at the surface increase as the slip parameter increases

    Advanced Microwave Circuits and Systems

    Get PDF

    Circuit Design And Reliability Of A Cmos Receiver

    Get PDF
    This dissertation explores CMOS RF design and reliability for portable wireless receivers. The objective behind this research is to achieve an increase in integration level, and gain more understanding for RF reliability. The fields covered include device, circuit and system. What is under investigation is a multi-band multi-mode receiver with GSM, DCS-1800 and CDMA compatibility. To my understanding, GSM and CDMA dual-mode mobile phones are progressively investigated in industries, and few commercial products are available. The receiver adopts direct conversion architecture. Some improved circuit design methods are proposed, for example, for low noise amplifier (LNA). Except for band filters, local oscillators, and analog-digital converters which are usually implemented by COTS SAW filters and ICs, all the remaining blocks such as switch, LNA, mixer, and local oscillator are designed in MOSIS TSMC 0.35[micro]m technology in one chip. Meanwhile, this work discusses related circuit reliability issues, which are gaining more and more attention. Breakdown (BD) and hot carrier (HC) effects are important issues in semiconductor industry. Soft-breakdown (SBD) and HC effects on device and RF performance has been reported. Hard-breakdown (HBD) effects on digital circuits have also been investigated. This work uniquely address HBD effects on the RF device and circuit performance, taking low noise amplifier and power amplifier as targets

    Rf Power Amplifier And Oscillator Design For Reliability And Variability

    Get PDF
    CMOS RF circuit design has been an ever-lasting research field. It gained so much attention since RF circuits have high mobility and wide band efficiency, while CMOS technology has the advantage of low cost and better capability of integration. At the same time, IC circuits never stopped scaling down for the recent many decades. Reliability issues with RF circuits have become more and more severe with device scaling down: reliability effects such as gate oxide break down, hot carrier injection, negative bias temperature instability, have been amplified as the device size shrinks. Process variability issues also become more predominant as the feature size decreases. With these insights provided, reliability and variability evaluations on typical RF circuits and possible compensation techniques are highly desirable. In this work, a class E power amplifier is designed and laid out using TSMC 0.18 µm RF technology and the chip was fabricated. Oxide stress and hot electron tests were carried out at elevated supply voltage, fresh measurement results were compared with different stress conditions after 10 hours. Test results matched very well with mixed mode circuit simulations, proved that hot carrier effects degrades PA performances like output power, power efficiency, etc. Self- heating effects were examined on a class AB power amplifier since PA has high power operations. Device temperature simulation was done both in DC and mixed mode level. Different gate biasing techniques were analyzed and their abilities to compensate output power were compared. A simple gate biasing circuit turned out to be efficient to compensate selfheating effects under different localized heating situations. iv Process variation was studied on a classic Colpitts oscillator using Monte-Carlo simulation. Phase noise was examined since it is a key parameter in oscillator. Phase noise was modeled using analytical equations and supported by good match between MATLAB results and ADS simulation. An adaptive body biasing circuit was proposed to eliminate process variation. Results from probability density function simulation demonstrated its capability to relieve process variation on phase noise. Standard deviation of phase noise with adaptive body bias is much less than the one without compensation. Finally, a robust, adaptive design technique using PLL as on-chip sensor to reduce Process, Voltage, Temperature (P.V.T.) variations and other aging effects on RF PA was evaluated. The frequency and phase of ring oscillator need to be adjusted to follow the frequency and phase of input in PLL no matter how the working condition varies. As a result, the control signal of ring oscillator has to fluctuate according to the working condition, reflecting the P.V.T changes. RF circuits suffer from similar P.V.T. variations. The control signal of PLL is introduced to RF circuits and converted to the adaptive tuning voltage for substrate bias. Simulation results illustrate that the PA output power under different variations is more flat than the one with no compensation. Analytical equations show good support to what has been observed

    A review of technologies and design techniques of millimeter-wave power amplifiers

    Get PDF
    his article reviews the state-of-the-art millimeter-wave (mm-wave) power amplifiers (PAs), focusing on broadband design techniques. An overview of the main solid-state technologies is provided, including Si, gallium arsenide (GaAs), GaN, and other III-V materials, and both field-effect and bipolar transistors. The most popular broadband design techniques are introduced, before critically comparing through the most relevant design examples found in the scientific literature. Given the wide breadth of applications that are foreseen to exploit the mm-wave spectrum, this contribution will represent a valuable guide for designers who need a single reference before adventuring in the challenging task of the mm-wave PA design

    RF Circuit Designs for Reliability and Process Variability Resilience

    Get PDF
    Complementary metal oxide semiconductor (CMOS) radio frequency (RF) circuit design has been an ever-lasting research field. It has gained so much attention since RF circuits offer high mobility and wide-band efficiency, while CMOS technology provides the advantage of low cost and high integration capability. At the same time, CMOS device size continues to scale to the nanometer regime. Reliability issues with RF circuits have become more challenging than ever before. Reliability mechanisms, such as gate oxide breakdown, hot carrier injection, negative bias temperature instability, have been amplified as the device size shrinks. In addition, process variability becomes a new design paradigm in modern RF circuits. In this Ph.D. work, a class F power amplifier (PA) was designed and analyzed using TSMC 180nm process technology. Its pre-layout and post-layout performances were compared. Post-layout parasitic effect decreases the output power and power-added efficiency. Physical insight of hot electron impact ionization and device self-heating was examined using the mixed-mode device and circuit simulation to mimic the circuit operating environment. Hot electron effect increases the threshold voltage and decreases the electron mobility of an n-channel transistor, which in turn decreases the output power and power-added efficiency of the power amplifier, as evidenced by the RF circuit simulation results. The device self-heating also reduces the output power and power-added efficiency of the PA. The process, voltage, and temperature (PVT) effects on a class AB power amplifier were studied. A PVT compensation technique using a current-source as an on-chip sensor was developed. The adaptive body bias design with the current sensing technique makes the output power and power-added efficiency much less sensitive to process variability, supply voltage variation, and temperature fluctuation, predicted by our derived analytical equations which are also verified by Agilent Advanced Design System (ADS) circuit simulation. Process variations and hot electron reliability on the mixer performance were also evaluated using different process corner models. The conversion gain and noise figure were modeled using analytical equations, supported by ADS circuit simulation results. A process invariant current source circuit was developed to eliminate process variation effect on circuit performance. Our conversion gain, noise figure, and output power show robust performance against PVT variations compared to those of a traditional design without using the current sensor, as evidenced by Monte Carlo statistical simulation. Finally, semiconductor process variations and hot electron reliability on the LC-voltage controlled oscillator (VCO) performance was evaluated using different process models. In our newly designed VCO, the phase noise and power consumptions are resilient against process variation effect due to the use of on-chip current sensing and compensation. Our Monte-Carlo simulation and analysis demonstrate that the standard deviation of phase noise in the new VCO design reduces about five times than that of the conventional design
    • …
    corecore