12,839 research outputs found

    A survey of carbon nanotube interconnects for energy efficient integrated circuits

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    This article is a review of the state-of-art carbon nanotube interconnects for Silicon application with respect to the recent literature. Amongst all the research on carbon nanotube interconnects, those discussed here cover 1) challenges with current copper interconnects, 2) process & growth of carbon nanotube interconnects compatible with back-end-of-line integration, and 3) modeling and simulation for circuit-level benchmarking and performance prediction. The focus is on the evolution of carbon nanotube interconnects from the process, theoretical modeling, and experimental characterization to on-chip interconnect applications. We provide an overview of the current advancements on carbon nanotube interconnects and also regarding the prospects for designing energy efficient integrated circuits. Each selected category is presented in an accessible manner aiming to serve as a survey and informative cornerstone on carbon nanotube interconnects relevant to students and scientists belonging to a range of fields from physics, processing to circuit design

    Phonon anharmonicities in graphite and graphene

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    We determine from first-principles the finite-temperature properties--linewidths, line shifts, and lifetimes--of the key vibrational modes that dominate inelastic losses in graphitic materials. In graphite, the phonon linewidth of the Raman-active E2g mode is found to decrease with temperature; such anomalous behavior is driven entirely by electron-phonon interactions, and does not appear in the nearly-degenerate infrared-active E1u mode. In graphene, the phonon anharmonic lifetimes and decay channels of the A'1 mode at K dominate over E2g at G and couple strongly with acoustic phonons, highlighting how ballistic transport in carbon-based interconnects requires careful engineering of phonon decays and thermalization.Comment: 5 pages, 4 figures; typos corrected and reference adde

    The application of encapsulation material stability data to photovoltaic module life assessment

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    For any piece of hardware that degrades when subject to environmental and application stresses, the route or sequence that describes the degradation process may be summarized in terms of six key words: LOADS, RESPONSE, CHANGE, DAMAGE, FAILURE, and PENALTY. Applied to photovoltaic modules, these six factors form the core outline of an expanded failure analysis matrix for unifying and integrating relevant material degradation data and analyses. An important feature of this approach is the deliberate differentiation between factors such as CHANGE, DAMAGE, and FAILURE. The application of this outline to materials degradation research facilitates the distinction between quantifying material property changes and quantifying module damage or power loss with their economic consequences. The approach recommended for relating material stability data to photovoltaic module life is to use the degree of DAMAGE to (1) optical coupling, (2) encapsulant package integrity, (3) PV circuit integrity or (4) electrical isolation as the quantitative criterion for assessing module potential service life rather than simply using module power loss

    Modeling of thermally induced skew variations in clock distribution network

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    Clock distribution network is sensitive to large thermal gradients on the die as the performance of both clock buffers and interconnects are affected by temperature. A robust clock network design relies on the accurate analysis of clock skew subject to temperature variations. In this work, we address the problem of thermally induced clock skew modeling in nanometer CMOS technologies. The complex thermal behavior of both buffers and interconnects are taken into account. In addition, our characterization of the temperature effect on buffers and interconnects provides valuable insight to designers about the potential impact of thermal variations on clock networks. The use of industrial standard data format in the interface allows our tool to be easily integrated into existing design flow
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