Introduction to the special section on dependable network computing

Dependable network computing is becoming a key part of our daily economic and social life. Every day, millions of users and businesses are utilizing the Internet infrastructure for real-time electronic commerce transactions, scheduling important events, and building relationships. While network traffic and the number of users are rapidly growing, the mean-time between failures (MTTF) is surprisingly short; according to recent studies, in the majority of Internet backbone paths, the MTTF is 28 days. This leads to a strong requirement for highly dependable networks, servers, and software systems. The challenge is to build interconnected systems, based on available technology, that are inexpensive, accessible, scalable, and dependable. This special section provides insights into a number of these exciting challenges

FirstLight: Pluggable Optical Interconnect Technologies for Polymeric Electro-Optical Printed Circuit Boards in Data Centers

The protocol data rate governing data storage devices will increase to over 12 Gb/s by 2013 thereby imposing unmanageable cost and performance burdens on future digital data storage systems. The resulting performance bottleneck can be substantially reduced by conveying high-speed data optically instead of electronically. A novel active pluggable 82.5 Gb/s aggregate bit rate optical connector technology, the design and fabrication of a compact electro-optical printed circuit board to meet exacting specifications, and a method for low cost, high precision, passive optical assembly are presented. A demonstration platform was constructed to assess the viability of embedded electro-optical midplane technology in such systems including the first ever demonstration of a pluggable active optical waveguide printed circuit board connector. High-speed optical data transfer at 10.3125 Gb/s was demonstrated through a complex polymer waveguide interconnect layer embedded into a 262 mm × 240 mm × 4.3 mm electro-optical midplane. Bit error rates of less than 10-12 and optical losses as low as 6 dB were demonstrated through nine multimode polymer wave guides with an aggregate data bandwidth of 92.8125 Gb/s

FirstLight: Pluggable Optical Interconnect Technologies for Polymeric Electro-Optical Printed Circuit Boards in Data Centers

The protocol data rate governing data storage devices will increase to over 12 Gb/s by 2013 thereby imposing unmanageable cost and performance burdens on future digital data storage systems. The resulting performance bottleneck can be substantially reduced by conveying high-speed data optically instead of electronically. A novel active pluggable 82.5 Gb/s aggregate bit rate optical connector technology, the design and fabrication of a compact electro-optical printed circuit board to meet exacting specifications, and a method for low cost, high precision, passive optical assembly are presented. A demonstration platform was constructed to assess the viability of embedded electro-optical midplane technology in such systems including the first ever demonstration of a pluggable active optical waveguide printed circuit board connector. High-speed optical data transfer at 10.3125 Gb/s was demonstrated through a complex polymer waveguide interconnect layer embedded into a 262 mm × 240 mm × 4.3 mm electro-optical midplane. Bit error rates of less than 10-12 and optical losses as low as 6 dB were demonstrated through nine multimode polymer wave guides with an aggregate data bandwidth of 92.8125 Gb/s

Phase and amplitude pre-emphasis techniques for low-power serial links

A novel approach to equalization of high-speed serial links combines both amplitude pre-emphasis to correct for intersymbol interference and phase pre-emphasis to compensate for deterministic jitter, in particular, data-dependent jitter. Phase pre-emphasis augments the performance of low power transmitters in bandwidth-limited channels. The transmitter circuit is implemented in a 90-nm bulk CMOS process and reduces power consumption by pushing CMOS static logic to the output stage, a 4:1 output multiplexer. The received signal jitter over a cable is reduced from 16.15 ps to 10.29 ps with only phase pre-emphasis at the transmitter. The jitter is reduced by 3.6 ps over an FR-4 backplane interconnect. A transmitter without phase pre-emphasis consumes 18 mW of power at 6Gb/s and 600mVpp output swing, a power budget of 3mW/Gb/s, while a transmitter with phase pre-emphasis consumes 24mW, a budget of 4 mW/Gb/s

Electricity from photovoltaic solar cells: Flat-Plate Solar Array Project final report. Volume VI: Engineering sciences and reliability

The Flat-Plate Solar Array (FSA) Project, funded by the U.S. Government and managed by the Jet Propulsion Laboratory, was formed in 1975 to develop the module/array technology needed to attain widespread terrestrial use of photovoltaics by 1985. To accomplish this, the FSA Project established and managed an Industry, University, and Federal Government Team to perform the needed research and development. This volume of the series of final reports documenting the FSA Project deals with the Project's activities directed at developing the engineering technology base required to achieve modules that meet the functional, safety and reliability requirements of large-scale terrestrial photovoltaic systems applications. These activities included: (1) development of functional, safety, and reliability requirements for such applications; (2) development of the engineering analytical approaches, test techniques, and design solutions required to meet the requirements; (3) synthesis and procurement of candidate designs for test and evaluation; and (4) performance of extensive testing, evaluation, and failure analysis to define design shortfalls and, thus, areas requiring additional research and development. During the life of the FSA Project, these activities were known by and included a variety of evolving organizational titles: Design and Test, Large-Scale Procurements, Engineering, Engineering Sciences, Operations, Module Performance and Failure Analysis, and at the end of the Project, Reliability and Engineering Sciences. This volume provides both a summary of the approach and technical outcome of these activities and provides a complete Bibliography (Appendix A) of the published documentation covering the detailed accomplishments and technologies developed

Current and Future Research Trends in Substrate Integrated Waveguide Technology

Substrate Integrated Waveguide (SIW) technology is the most promising candidate for the implementation of millimeter-wave (mm-wave) integrated circuits and systems for the next decade. Based on planar dielectric substrates with top and bottom metal layers perforated with metalized holes, SIW structures offer a compact, low loss, flexible, and cost-effective solution for integrating active circuits, passive components and radiating elements on the same substrate. This paper presents an overview of the current status and future trends of academic and industrial research on SIW technology. The historical development of SIW components and circuits is briefly outlined, and the current research topics are discussed: they include the development of numerical techniques for the modeling and design of SIW components, the investigation of novel compact and broadband interconnects, the determination of design solutions for loss minimization. Future research trends are also discussed: they mainly aim at the implementation of SIW components at higher frequency (60-350 GHz) and the integration of complete Systems-on-Substrate (SoS)

Committee machines -- a universal method to deal with non-idealities in memristor-based neural networks

Artificial neural networks are notoriously power- and time-consuming when implemented on conventional von Neumann computing systems. Consequently, recent years have seen an emergence of research in machine learning hardware that strives to bring memory and computing closer together. A popular approach is to realise artificial neural networks in hardware by implementing their synaptic weights using memristive devices. However, various device- and system-level non-idealities usually prevent these physical implementations from achieving high inference accuracy. We suggest applying a well-known concept in computer science -- committee machines -- in the context of memristor-based neural networks. Using simulations and experimental data from three different types of memristive devices, we show that committee machines employing ensemble averaging can successfully increase inference accuracy in physically implemented neural networks that suffer from faulty devices, device-to-device variability, random telegraph noise and line resistance. Importantly, we demonstrate that the accuracy can be improved even without increasing the total number of memristors.Comment: 22 pages, 18 figures, 4 table

Committee Machines—A Universal Method to Deal with Non-Idealities in Memristor-Based Neural Networks

Arti ficial neural networks are notoriously power- and time-consuming when implemented on conventional von Neumann computing systems. Consequently, recent years have seen an emergence of research in machine learning hardware that strives to bring memory and computing closer together. A popular approach is to realise artifi cial neural networks in hardware by implementing their synaptic weights using memristive devices. However, various device- and system-level non-idealities usually prevent these physical implementations from achieving high inference accuracy. We suggest applying a well-known concept in computer science|committee machines|in the context of memristor-based neural networks. Using simulations and experimental data from three different types of memristive devices, we show that committee machines employing ensemble averaging can successfully increase inference accuracy in physically implemented neural networks that suffer from faulty devices, device-to-device variability, random telegraph noise and line resistance. Importantly, we demonstrate that the accuracy can be improved even without increasing the total number of memristors

Committee Machines—A Universal Method to Deal with Non-Idealities in RRAM-Based Neural Networks

Artificial neural networks (ANNs) are notoriously power- and time-consuming when implemented on conventional von Neumann computing systems. Recent years have seen an emergence of research in hardware that strives to break the bottleneck of von Neumann architecture and optimise the data flow; namely to bring memory and computing closer together. One of the most often suggested solutions is the physical implementation of ANNs in which their synaptic weights are realised with analogue resistive devices, such as resistive random-access memory (RRAM). However, various device- and system-level non-idealities usually prevent these physical implementations from achieving high inference accuracy. We suggest applying a well-known concept in computer science -- committee machine (CM) -- in the context of RRAM-based neural networks. Using simulations and experimental data from three different types of RRAM devices, we show that CMs employing ensemble averaging can successfully increase inference accuracy in physically implemented neural networks that suffer from faulty devices, programming non-linearities, random telegraph noise, cycle-to-cycle variability and line resistance. Importantly, we show that the accuracy can be improved even without increasing the number of devices

Progressive congestion management based on packet marking and validation techniques

© 2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Congestion management in multistage interconnection networks is a serious problem, which is not solved completely. In order to avoid the degradation of network performance when congestion appears, several congestion management mechanisms have been proposed. Most of these mechanisms are based on explicit congestion notification. For this purpose, switches detect congestion and depending on the applied strategy, packets are marked to warn the source hosts. In response, source hosts apply some corrective actions to adjust their packet injection rate. Although these proposals seem quite effective, they either exhibit some drawbacks or are partial solutions. Some of them introduce some penalties over the flows not responsible for congestion, whereas others can cope only with congestion situations that last for a short time. In this paper, we present an overview of the different strategies to detect and correct congestion in multistage interconnection networks, and propose a new mechanism referred to as Marking and Validation Congestion Management (MVCM), targeted to this kind of lossless networks, and based on a more refined packet marking strategy combined with a fair set of corrective actions, that makes the mechanism able to effectively manage congestion regardless of the congestion degree. Evaluation results show the effectiveness and robustness of the proposed mechanism.This work was supported by the Spanish MEC and MICINN, as well as European Commission FEDER funds, under Grants CSD2006-00046 and TIN2009-14475-C04-01.Ferrer Pérez, JL.; Baydal Cardona, ME.; Robles Martínez, A.; López Rodríguez, PJ.; Duato Marín, JF. (2012). Progressive congestion management based on packet marking and validation techniques. IEEE Transactions on Computers. 61(9):1296-1309. doi:10.1109/TC.2011.146S1296130961