Intrinsic Reliability improvement in Biaxially Strained SiGe p-MOSFETs

In this letter we not only show improvement in the performance but also in the reliability of 30nm thick biaxially strained SiGe (20%Ge) channel on Si p-MOSFETs. Compared to Si channel, strained SiGe channel allows larger hole mobility ({\mu}h) in the transport direction and alleviates charge flow towards the gate oxide. {\mu}h enhancement by 40% in SiGe and 100% in Si-cap SiGe is observed compared to the Si hole universal mobility. A ~40% reduction in NBTI degradation, gate leakage and flicker noise (1/f) is observed which is attributed to a 4% increase in the hole-oxide barrier height ({\phi}) in SiGe. Similar field acceleration factor ({\Gamma}) for threshold voltage shift ({\Delta}VT) and increase in noise ({\Delta}SVG) in Si and SiGe suggests identical degradation mechanisms.Comment: 4 figures, 3 pages, accepted for publication in IEEE ED

MOSFET Channel Engineering using Strained Si, SiGe, and Ge Channels

Biaxial tensile strained Si grown on SiGe virtual substrates will be incorporated into future generations of CMOS technology due to the lack of performance increase with scaling. Compressively strained Ge-rich alloys with high hole mobilities can also be grown on relaxed SiGe. We review progress in strained Si and dual channel heterostructures, and also introduce high hole mobility digital alloy heterostructures. By optimizing growth conditions and understanding the physics of hole and electron transport in these devices, we have fabricated nearly symmetric mobility p- and n-MOSFETs on a common Si₀.₅Ge₀.₅ virtual substrate.Singapore-MIT Alliance (SMA

Hole transport in strained SiGe-channel MOSFETs : velocity in scaled devices and mobility under applied mechanical strain

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.Cataloged from PDF version of thesis.Includes bibliographical references (p. 153-167).Since the 90 nm CMOS technology node, geometric scaling of CMOS has been supplemented with strain to boost transistor drive current. Future CMOS technology nodes (i.e. beyond the 32 nm node) will require more significant changes to continue improvements in transistor performance. Novel CMOS channel materials and device architectures are one option for enhancing carrier transport and increasing device performance. In this work strained SiGe and Ge are examined as a means of increasing the drive current in deeply scaled CMOS. As part of this work a novel high mobility strained-Ge on-insulator substrate has been developed, and the hole transport characteristics of short channel and asymmetrically strained-SiGe channel p-MOSFETs have been explored. A thin-body biaxial compressive strained-Si/strained-Ge heterostructure on-insulator (HOI) substrate has been developed, which combines the electrostatic benefits of the thin-body architecture with the transport benefits of biaxial compressive strain. A novel Germanium on Silicon growth method and a low temperature bond and etch-back process have been developed to enable Ge HOI fabrication. P-MOSFETs were also fabricated using these substrates and the hole mobility characteristics were studied. The hole mobility and velocity characteristics of short channel biaxial compressive strained-Si 45 Geo.55 p-MOSFETs on-insulator have also been examined. Devices with gate lengths down to 65 nm were fabricated. The short channel mobility characteristics were extracted and a 2.4x hole mobility enhancement relative to relaxed-Si was observed. The measured hole velocity enhancement is more modest at about 1.2x. Band structure and ballistic velocity simulations suggest that a more substantial velocity improvement can be expected with the incorporation of added longitudinal uniaxial compressive strain in the SiGe channel. The hole mobility characteristics of biaxial strained SiGe and Ge p-MOSFETs with applied uniaxial strain are also studied. The hole mobility in biaxial compressive strained SiGe is already enhanced relative to relaxed Si. It is observed that this mobility enhancement increases further with the application of longitudinal uniaxial compressive strain. Since hole mobility and velocity are correlated through their dependence on the hole effective mass, a mass driven increase in mobility with applied uniaxial strain should result in an increase in velocity. Simulations have also been performed to estimate the hole effective mass change in asymmetric strained SiGe. Finally the piezo resistance coefficients of strained SiGe are extracted and found to be larger than in Si.by Leonardo Gomez.Ph.D

Compressively strained Ge trigate p-MOSFETs

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.Includes bibliographical references (p. 71-74).State of the art MOSFET performance is limited by the electronic properties of the material that is being used, silicon (Si). In order to continue performance enhancements, different materials are being studied for the extension of Si CMOS. One of the materials of interest, particularly for p-MOSFETs, is Ge because it has very high intrinsic hole mobility. Further improvements in hole mobility can be achieved by straining the material. At the same time it is important to study strained Ge transport in device architectures such as trigate MOSFETs. These devices offer the potential for better scalability than planar MOSFETs via improved electrostatics. The investigation of hole mobility in strained Ge trigate ("nanowire") p- MOSFETs is the focus of this work. To study the effects of strain on Ge as a p-channel material, Strained Germanium Directly on Insulator (SGDOI) substrates were fabricated. The substrates were strained to ~2.4% using lattice mismatch which originates from the growth of Ge on a relaxed Si₀.₆Ge₀.₄ epitaxial layer. A biaxially strained SGDOI substrate was patterned to form Ge nanowires which were measured by Raman spectroscopy to investigate the strain relaxation from the free surface. Another SGDOI substrate was used for nanowire trigate p-MOSFET fabrication. The semiconductor layer structure for the devices consisted of 10 nm-thick strained-Ge with a 5 nm-thick strained-Si cap. On-chip biaxially strained MOSFETs were compared to asymmetrically strained Ge nanowire devices. Significantly improved mobilities (~2x) were observed for nanowire devices with a width of 49 nm compared to the on-chip biaxially strained Ge controls. These mobilities are ~15x over Si universal hole mobility. The impact of strain on the transport of holes in long channel devices is also studied as a function of nanowire width. Mobility decreased for narrower nanowire MOSFETs, likely associated with increased sidewall line edge roughness scattering in narrow lines.by Winston Chern.S.M

Indication of Non-equilibrium Transport in SiGe p-MOSFETs

No abstract avaliable

Nonequilibrium hole transport in deep sub-micron well-tempered Si p-MOSFETs

Using 2D full-band MC simulations the authors study nonequilibrium transport effects and the performance potential of well tempered Si p-channel MOSFETs covering gate lengths ranging from 90nm to 25nm. By comparing MC simulations with carefully calibrated drift diffusion (DD) simulations of the same devices, they provide a quantitative estimate of the importance and the influence of nonequilibrium transport on the device performance

Increase in the random dopant induced threshold fluctuations and lowering in sub-100 nm MOSFETs due to quantum effects: a 3-D density-gradient simulation study

In this paper, we present a detailed simulation study of the influence of quantum mechanical effects in the inversion layer on random dopant induced threshold voltage fluctuations and lowering in sub-100 mn MOSFETs. The simulations have been performed using a three-dimensional (3-D) implementation of the density gradient (DG) formalism incorporated in our established 3-D atomistic simulation approach. This results in a self-consistent 3-D quantum mechanical picture, which implies not only the vertical inversion layer quantization but also the lateral confinement effects related to current filamentation in the “valleys” of the random potential fluctuations. We have shown that the net result of including quantum mechanical effects, while considering statistical dopant fluctuations, is an increase in both threshold voltage fluctuations and lowering. At the same time, the random dopant induced threshold voltage lowering partially compensates for the quantum mechanical threshold voltage shift in aggressively scaled MOSFETs with ultrathin gate oxides