21 research outputs found
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Cross-Layer Platform for Dynamic, Energy-Efficient Optical Networks
The design of the next-generation Internet infrastructure is driven by the need to sustain the massive growth in bandwidth demands. Novel, energy-efficient, optical networking technologies and architectures are required to effectively meet the stringent performance requirements with low cost and ultrahigh energy efficiencies. In this thesis, a cross-layer communications platform is proposed to enable greater intelligence and functionality on the physical layer. Providing the optical layer with advanced networking capabilities will facilitate the dynamic management and optimization of optical switching based on performance monitoring measurements and higher-layer attributes. The cross-layer platform aims to create a new framework for networks to incorporate packet-scale measurement subsystems and techniques for monitoring the health of the optical channel. This will allow for quality-of-service- and energy-aware routing schemes, as well as an enhanced awareness of the optical data signals. This thesis first presents the design and development of an optical packet switching fabric. Leveraging a networking test-bed environment to validate networking hypotheses, advanced switching functionalities are demonstrated, including the support for quality-of-service based routing and packet multicasting. The investigated cross-layering is based on emerging optical technologies, enabling packet protection techniques and packet-rate switching fabric reconfiguration. Coupled with fast performance monitoring, the platform will achieve significant performance gains within the endeavor of all-optical switching. Allowing for a more intelligent, programmable optical layer aims to support greater flexibility with respect to bandwidth allocation and potentially a significant reduction in the network's energy consumption. The ultimate deliverable of this work is a high-performance, cross-layer enabled optical network node. The experimental demonstration of an initial prototype creates a dynamic network element with distributed control plane management, featuring fast packet-rate optical switching capabilities and embedded physical-layer performance monitoring modules. The cross-layer box enables an intelligent traffic delivery system that can dynamically manipulate optical switching on a packet-granular scale. With the goal of achieving advanced multi-layer routing and control algorithms, the network node requires an intelligent co-optimization across all the layers. The proposed cross-layer design should drive optical technologies and architectures in an innovative way, in order to fulfill the void between the design of basic photonic devices and the networking protocols that use them. The performance of the entire network -- from the optical components, to the routing algorithms and user applications -- should be optimized in concert. This contribution to the area of cross-layer network design creates an adaptable optical pipe that is extremely flexible and intelligent aware of both the physical optical signals and higher-layer requirements. The impact of this work will be seen in the realization of dynamic, energy-efficient optical communication links in future networking infrastructures
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High Performance Silicon Photonic Interconnected Systems
Advances in data-driven applications, particularly artificial intelligence and deep learning, are driving the explosive growth of computation and communication in today’s data centers and high-performance computing (HPC) systems. Increasingly, system performance is not constrained by the compute speed at individual nodes, but by the data movement between them. This calls for innovative architectures, smart connectivity, and extreme bandwidth densities in interconnect designs. Silicon photonics technology leverages mature complementary metal-oxide-semiconductor (CMOS) manufacturing infrastructure and is promising for low cost, high-bandwidth, and reconfigurable interconnects. Flexible and high-performance photonic switched architectures are capable of improving the system performance. The work in this dissertation explores various photonic interconnected systems and the associated optical switching functionalities, hardware platforms, and novel architectures. It demonstrates the capabilities of silicon photonics to enable efficient deep learning training.
We first present field programmable gate array (FPGA) based open-loop and closed-loop control for optical spectral-and-spatial switching of silicon photonic cascaded micro-ring resonator (MRR) switches. Our control achieves wavelength locking at the user-defined resonance of the MRR for optical unicast, multicast, and multiwavelength-select functionalities. Digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) are necessary for the control of the switch. We experimentally demonstrate the optical switching functionalities using an FPGA-based switch controller through both traditional multi-bit DAC/ADC and novel single-wired DAC/ADC circuits. For system-level integration, interfaces to the switch controller in a network control plane are developed. The successful control and the switching functionalitiesachieved are essential for system-level architectural innovations as presented in the following sections.
Next, this thesis presents two novel photonic switched architectures using the MRR-based switches. First, a photonic switched memory system architecture was designed to address memory challenges in deep learning. The reconfigurable photonic interconnects provide scalable solutions and enable efficient use of disaggregated memory resources for deep learning training. An experimental testbed was built with a processing system and two remote memory nodes using silicon photonic switch fabrics and system performance improvements were demonstrated. The collective results and existing high-bandwidth optical I/Os show the potential of integrating the photonic switched memory to state-of-the-art processing systems. Second, the scaling trends of deep learning models and distributed training workloads are challenging network capacities in today’s data centers and HPCs. A system architecture that leverages SiP switch-enabled server regrouping is proposed to tackle the challenges and accelerate distributed deep learning training. An experimental testbed with a SiP switch-enabled reconfigurable fat tree topology was built to evaluate the network performance of distributed ring all-reduce and parameter server workloads. We also present system-scale simulations. Server regrouping and bandwidth steering were performed on a large-scale tapered fat tree with 1024 compute nodes to show the benefits of using photonic switched architectures in systems at scale.
Finally, this dissertation explores high-bandwidth photonic interconnect designs for disaggregated systems. We first introduce and discuss two disaggregated architectures leveraging extreme high bandwidth interconnects with optically interconnected computing resources. We present the concept of rack-scale graphics processing unit (GPU) disaggregation with optical circuit switches and electrical aggregator switches. The architecture can leverage the flexibility of high bandwidth optical switches to increase hardware utilization and reduce application runtimes. A testbed was built to demonstrate resource disaggregation and defragmentation. In addition, we also present an extreme high-bandwidth optical interconnect accelerated low-latency communication architecture for deep learning training. The disaggregated architecture utilizes comb laser sources and MRR-based cross-bar switching fabrics to enable an all-to-all high bandwidth communication with a constant latency cost for distributed deep learning training. We discuss emerging technologies in the silicon photonics platform, including light source, transceivers, and switch architectures, to accommodate extreme high bandwidth requirements in HPC and data center environments. A prototype hardware innovation - Optical Network Interface Cards (comprised of FPGA, photonic integrated circuits (PIC), electronic integrated circuits (EIC), interposer, and high-speed printed circuit board (PCB)) is presented to show the path toward fast lanes for expedited execution at 10 terabits.
Taken together, the work in this dissertation demonstrates the capabilities of high-bandwidth silicon photonic interconnects and innovative architectural designs to accelerate deep learning training in optically connected data center and HPC systems
Meeting the requirements to deploy cloud RAN over optical networks
Radio access network (RAN) cost savings are expected in future cloud RAN (C-RAN). In contrast to traditional distributed RAN architectures, in C-RAN, remote radio heads (RRHs) from different sites can share baseband processing resources from virtualized baseband unit pools placed in a few central locations (COs). Due to the stringent requirements of the several interfaces needed in C-RAN, optical networks have been proposed to support C-RAN. One of the key elements that needs to be considered are optical transponders. Specifically, sliceable bandwidth-variable transponders (SBVTs) have recently shown many advantages for core optical transport networks. In this paper, we study the connectivity requirements of C-RAN applications and conclude that dynamicity, fine granularity, and elasticity are needed. However, there is no SBVT implementation that supports those requirements, and thus, we propose and assess an SBVT architecture based on dynamic optical arbitrary generation/measurement. We consider different long-term evolution-advanced configurations and study the impact of the centralization level in terms of the capital expense and operating expense. An optimization problem is modeled to decide which COs should be equipped and which equipment, including transponders, needs to be installed. The results show noticeable cost savings from installing the proposed SBVTs compared to installing fixed transponders. Finally, compared to the maximum centralization level, remarkable cost savings are shown when a lower level of centralization is considered.Peer ReviewedPostprint (author's final draft
A scalable silicon photonic chip-scale optical switch for high performance computing systems
This paper discusses the architecture and provides performance studies of a silicon photonic chip-scale optical switch for scalable interconnect network in high performance computing systems. The proposed switch exploits optical wavelength parallelism and wavelength routing characteristics of an Arrayed Waveguide Grating Router (AWGR) to allow contention resolution in the wavelength domain. Simulation results from a cycle-accurate network simulator indicate that, even with only two transmitter/receiver pairs per node, the switch exhibits lower end-to-end latency and higher throughput at high (> 90%) input loads compared with electronic switches. On the device integration level, we propose to integrate all the components (ring modulators, photodetectors and AWGR) on a CMOS-compatible silicon photonic platform to ensure a compact, energy efficient and cost-effective device. We successfully demonstrate proof-of-concept routing functions on an 8 x 8 prototype fabricated using foundry services provided by OpSIS-IME. (C) 2013 Optical Society of Americ
Characterization, design and re-optimization on multi-layer optical networks
L'augment de volum de tràfic IP provocat per l'increment de serveis multimèdia com HDTV o vídeo conferència planteja nous reptes als operadors de xarxa per tal de proveir transmissió de dades eficient. Tot i que les xarxes mallades amb multiplexació per divisió de longitud d'ona (DWDM) suporten connexions òptiques de gran velocitat, aquestes xarxes manquen de flexibilitat per suportar tràfic d’inferior granularitat, fet que provoca un pobre ús d'ample de banda. Per fer front al transport d'aquest tràfic heterogeni, les xarxes multicapa representen la millor solució.
Les xarxes òptiques multicapa permeten optimitzar la capacitat mitjançant l'empaquetament de connexions de baixa velocitat dins de connexions òptiques de gran velocitat. Durant aquesta operació, es crea i modifica constantment una topologia virtual dinàmica gràcies al pla de control responsable d’aquestes operacions. Donada aquesta dinamicitat, un ús sub-òptim de recursos pot existir a la xarxa en un moment donat. En aquest context, una re-optimizació periòdica dels recursos utilitzats pot ser aplicada, millorant així l'ús de recursos.
Aquesta tesi està dedicada a la caracterització, planificació, i re-optimització de xarxes òptiques multicapa de nova generació des d’un punt de vista unificat incloent optimització als nivells de capa física, capa òptica, capa virtual i pla de control. Concretament s'han desenvolupat models estadístics i de programació matemàtica i meta-heurístiques. Aquest objectiu principal s'ha assolit mitjançant cinc objectius concrets cobrint diversos temes oberts de recerca.
En primer lloc, proposem una metodologia estadística per millorar el càlcul del factor Q en problemes d'assignació de ruta i longitud d'ona considerant interaccions físiques (IA-RWA). Amb aquest objectiu, proposem dos models estadístics per computar l'efecte XPM (el coll d'ampolla en termes de computació i complexitat) per problemes IA-RWA, demostrant la precisió d’ambdós models en el càlcul del factor Q en escenaris reals de tràfic.
En segon lloc i fixant-nos a la capa òptica, presentem un nou particionament del conjunt de longituds d'ona que permet maximitzar, respecte el cas habitual, la quantitat de tràfic extra proveït en entorns de protecció compartida. Concretament, definim diversos models estadístics per estimar la quantitat de tràfic donat un grau de servei objectiu, i diferents models de planificació de xarxa amb l'objectiu de maximitzar els ingressos previstos i el valor actual net de la xarxa. Després de resoldre aquests problemes per xarxes reals, concloem que la nostra proposta maximitza ambdós objectius.
En tercer lloc, afrontem el disseny de xarxes multicapa robustes davant de fallida simple a la capa IP/MPLS i als enllaços de fibra. Per resoldre aquest problema eficientment, proposem un enfocament basat en sobre-dimensionar l'equipament de la capa IP/MPLS i recuperar la connectivitat i el comparem amb la solució convencional basada en duplicar la capa IP/MPLS. Després de comparar solucions mitjançant models ILP i heurístiques, concloem que la nostra solució permet obtenir un estalvi significatiu en termes de costos de desplegament.
Com a quart objectiu, introduïm un mecanisme adaptatiu per reduir l'ús de ports opto-electrònics (O/E) en xarxes multicapa sota escenaris de tràfic dinàmic. Una formulació ILP i diverses heurístiques són desenvolupades per resoldre aquest problema, que permet reduir significativament l’ús de ports O/E en temps molt curts.
Finalment, adrecem el problema de disseny resilient del pla de control GMPLS. Després de proposar un nou model analític per quantificar la resiliència en topologies mallades de pla de control, usem aquest model per proposar un problema de disseny de pla de control. Proposem un procediment iteratiu lineal i una heurística i els usem per resoldre instàncies reals, arribant a la conclusió que es pot reduir significativament la quantitat d'enllaços del pla de control sense afectar la qualitat de servei a la xarxa.The explosion of IP traffic due to the increase of IP-based multimedia services such as HDTV or video conferencing poses new challenges to network operators to provide a cost-effective data transmission. Although Dense Wavelength Division Multiplexing (DWDM) meshed transport networks support high-speed optical connections, these networks lack the flexibility to support sub-wavelength traffic leading to poor bandwidth usage. To cope with the transport of that huge and heterogeneous amount of traffic, multilayer networks represent the most accepted architectural solution.
Multilayer optical networks allow optimizing network capacity by means of packing several low-speed traffic streams into higher-speed optical connections (lightpaths). During this operation, a dynamic virtual topology is created and modified the whole time thanks to a control plane responsible for the establishment, maintenance, and release of connections. Because of this dynamicity, a suboptimal allocation of resources may exist at any time. In this context, a periodically resource reallocation could be deployed in the network, thus improving network resource utilization.
This thesis is devoted to the characterization, planning, and re-optimization of next-generation multilayer networks from an integral perspective including physical layer, optical layer, virtual layer, and control plane optimization. To this aim, statistical models, mathematical programming models and meta-heuristics are developed. More specifically, this main objective has been attained by developing five goals covering different open issues.
First, we provide a statistical methodology to improve the computation of the Q-factor for impairment-aware routing and wavelength assignment problems (IA-RWA). To this aim we propose two statistical models to compute the Cross-Phase Modulation variance (which represents the bottleneck in terms of computation time and complexity) in off-line and on-line IA-RWA problems, proving the accuracy of both models when computing Q-factor values in real traffic scenarios.
Second and moving to the optical layer, we present a new wavelength partitioning scheme that allows maximizing the amount of extra traffic provided in shared path protected environments compared with current solutions. Specifically, we define several statistical models to estimate the traffic intensity given a target grade of service, and different network planning problems for maximizing the expected revenues and net present value. After solving these problems for real networks, we conclude that our proposed scheme maximizes both revenues and NPV.
Third, we tackle the design of survivable multilayer networks against single failures at the IP/MPLS layer and WSON links. To efficiently solve this problem, we propose a new approach based on over-dimensioning IP/MPLS devices and lightpath connectivity and recovery and we compare it against the conventional solution based on duplicating backbone IP/MPLS nodes. After evaluating both approaches by means of ILP models and heuristic algorithms, we conclude that our proposed approach leads to significant CAPEX savings.
Fourth, we introduce an adaptive mechanism to reduce the usage of opto-electronic (O/E) ports of IP/MPLS-over-WSON multilayer networks in dynamic scenarios. A ILP formulation and several heuristics are developed to solve this problem, which allows significantly reducing the usage of O/E ports in very short running times.
Finally, we address the design of resilient control plane topologies in GMPLS-enabled transport networks. After proposing a novel analytical model to quantify the resilience in mesh control plane topologies, we use this model to propose a problem to design the control plane topology. An iterative model and a heuristic are proposed and used to solve real instances, concluding that a significant reduction in the number of control plane links can be performed without affecting the quality of service of the network
Microring-Resonator-Based Switch Architectures for Optical Networks
Integrated silicon photonics provides a promising platform for chip-based, high-speed optical signal processing due to its compatibility with complementary metal-oxide semiconductor (CMOS) fabrication processes. They are attracting significant research and development interest globally and making a huge impact on green information and communication technologies, and high-performance computing systems.
Microring resonators (MRRs) show the versatility to implement a variety of network functions, compact footprint, and complementary metal-oxide semiconductor compatibility, and demonstrate the viability applied in photonic integrated technologies for both chip level and board-to-board interconnects. Furthermore, MRRs have excellent wavelength selection properties and can be used to design tunable filters, modulators, wavelength converters, and switches that are critical components for optical interconnects.
The research work of this dissertation is focused on investigating how to develop MRR-based switches and switch architectures for possible applications not only in optical interconnection networks but also in flexible-grid on-chip networks for optical communication systems. The basic properties and performances of the MRR switches and the MRR switch architectures related to their applications in the networks are examined. In particular, how to design and how to configure high performance, bandwidth variable, low insertion loss, and weak crosstalk MRR-based switches and switch architectures are investigated for applications in optical interconnection networks and in flexible-grid on-chip networks for optical communication systems. The works include several parts as follows.
The physical characteristics of microring resonator switching devices are thoroughly analyzed using a model based on the field coupling matrix theory. The spectral response and insertion loss properties of these switching elements are simulated using the developed model. Then we investigate the optimal design of high-order MRR-based switch devices.
Spectral shaping of the passbands of microring resonator switches is studied. Multistage high-order microring resonator-based optical switch structures are proposed to achieve steep-edge flat-top spectral passband. Using the transfer matrix analysis model, the spectral response behaviors of the switch structures are simulated. The performances of the proposed multistage high-order microring resonator-based optical switch structures and the high-order microring-resonator-based optical switch structures without stages are studied and compared.
Two types of MRR-based switch architectures are proposed to realize variable output bandwidths varying from 0 to 4 THz. One consists of 320, 160, and 80 third-order MRR switches with -3 dB passband widths of 12.5, 25, and 50 GHz, respectively. Another one is two-stage switch structure. In the first stage there are 4 third-order MRR switches with the passband widths of 1 THz. In second stage, there are 80, 40, 20 third-order MRR switches with the passband widths of 12.5, 25, and 50 GHz, respectively. Their insertion losses and crosstalks in the worst cases are numerically analyzed and compared in order to show the feasibility for the architectures to be applied in flexible optical networks.
MRR-based bandwidth-variable wavelength selective switch architectures with multiple input and output ports are proposed for flexible optical networks. The light transmission behaviors of a 1 by N MRR-based WSS are analyzed in detail based on numerical simulation using transfer matrix theory. Two types of N by N MRR-based WSS architectures consisting of MRR-based WSSs and MRR-based WSSs, and MRR-based WSSs and optical couplers are proposed. The performances of the proposed architectures are studied.
Scalable optical interconnections based on MRRs are proposed, which consist mainly of microring resonator devices: microring lasers, microring switches, microring de-multiplexers, and integrated photo-dectors. Their throughput capacities, end-to-end time latencies, and transmission packet loss rates are evaluated using OMNet++.
In summary, the research of the dissertation contributes to develop high performance, variable bandwidth, low insertion loss, and low crosstalk MRR-based optical switches and switch architectures to adapt to dynamic source allocation of flexible-grid optical networks
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Photonic Interconnects Beyond High Bandwidth
The extraordinary growth of parallelism in high-performance computing requires efficient data communication for scaling compute performance. High-performance computing systems have been using photonic links for communication of large bandwidth-distance product during the last decade. Photonic interconnection networks, however, should not be a wire-for-wire replacement based on conventional electrical counterparts. Features of photonics beyond high bandwidth, such as transparent bandwidth steering, can implement important functionalities needed by applications. In another aspect, application characteristics can be exploited to design better photonic interconnects. Therefore, this thesis explores codesign opportunities at the intersection between photonic interconnect architectures and high-performance computing applications. The key accomplishments of this thesis, ranging from system level to node level, are as follows.
Chapter 2 presents a system-level architecture that leverages photonic switching to enable a reconfigurable interconnect. The architecture, called Flexfly, reconfigures the inter-group level of the widely-used Dragonfly topology using information about the application’s communication pattern. It can steal additional direct bandwidth for communication-intensive group pairs. Simulations with applications such as GTC, Nekbone and LULESH show up to 1.8x speedup over Dragonfly paired with UGAL routing, along with halved hop count and latency for cross-group messages. To demonstrate the effectiveness of our approach, we built a 32-node Flexfly prototype using a silicon photonic switch connecting four groups and demonstrated 820 ns interconnect reconfiguration time. This is the first demonstration of silicon photonic switching and bandwidth steering in a high-performance computing cluster.
Chapter 3 extends photonic switching to the node level and presents a reconfigurable silicon photonic memory interconnect for many-core architectures. The interconnect targets at important memory access issues, such as network-on-chip hot-spots and non-uniform memory access. Integrated with the processor through 2.5D/3D stacking, a fast-tunable silicon photonic memory tunnel can transparently direct traffic from any off-chip memory to any on-chip interface – thus alleviating the hot-spot and non-uniform access effects. We demonstrated the operation of our proposed architecture using a tunable laser, a 4-port silicon photonic switch (four wavelength-routed memory channels) and a 4x4 mesh network-on-chip synthesized by FPGA. The emulated system achieves a 15-ns channel switching time. Simulations based on a 12-core 4-memory model show that for such switching speeds the interconnect system can realize a 2x speedup for the STREAM benchmark in the hot-spot scenario and a reduction of execution time for data-intensive applications such as 3D stencil and K-means clustering by 23% and 17%, respectively.
Chapters 4 explores application-level characteristics that can be exploited to hide photonic path setup delays. In view of the frequent reuse of optical circuits by many applications, we proposed a circuit-cached scheme that amortizes the setup overhead by maximizing circuit reuses. In order to improve circuit “hit” rates, we developed a reuse-distance based replacement policy called “Farthest Next Use”. We further investigated the tradeoffs between the realized hit rate and energy consumption. Finally, we experimentally demonstrated the feasibility of the proposed concept using silicon photonic devices in an FPGA-controlled network testbed.
Chapter 5 proceeds to develop an application-guided circuit-prefetch scheme. By learning temporal locality and communication patterns from upper-layer applications, the scheme not only caches a set of circuits for reuses, but also proactively prefetches circuits based on predictions. We applied this technique to communication patterns from a spectrum of science and engineering applications. The results show that setup delays via circuit misses are significantly reduced, showing how the proposed technique can improve circuit switching in photonic interconnects