A Monolithic Gm-C Filter based Very Low Power, Programmable, and Multi-Channel Harmonic Discrimination System using Analog Signal Processing

A highly selective monolithic band-pass filter with programmable characteristics at micro-power operation is presented. Very low power signal processing is of great interest in wireless sensing and Internet-of-Things applications. This filter enables long-term battery powered operation of a highly selective harmonic signal discriminator for an analog signal processing system. The Gm-C biquadratic circuits were fabricated in a 0.18-μm [micrometer] CMOS process. Each 2nd-order biquad filter nominally consumes 20 μW [microwatt] and can be programmed for the desired gain (0db3dB), quality factor (5 to 20), and center-frequency from 1kHz to 100kHz. The 8th-order filter channel achieved an effective quality factor of 30 at 100kHz with an overall power consumption of 108 μW

Polyphase filter with parametric tuning

Tese de mestrado integrado. Engenharia Electrotécnica e de Computadores. Faculdade de Engenharia. Universidade do Porto. 201

Nonlinearity and noise modeling of operational transconductance amplifiers for continuous time analog filters

A general framework for performance optimization of continuous-time OTA-C (Operational Transconductance Amplifier-Capacitor) filters is proposed. Efficient procedures for evaluating nonlinear distortion and noise valid for any filter of arbitrary order are developed based on the matrix description of a general OTA-C filter model . Since these procedures use OTA macromodels, they can be used to obtain the results significantly faster than transistor-level simulation. In the case of transient analysis, the speed-up may be as much as three orders of magnitude without almost no loss of accuracy. This makes it possible to carry out direct numerical optimization of OTA-C filters with respect to important characteristics such as noise performance, THD, IM3, DR or SNR. On the other hand, the general OTA-C filter model allows us to apply matrix transforms that manipulate (rescale) filter element values and/or change topology without changing its transfer function. The above features are a basis to build automated optimization procedures for OTA-C filters. In particular, a systematic optimization procedure using equivalence transformations is proposed. The research also proposes suitable software implementations of the optimization process. The first part of the research proposes a general performance optimization procedure and to verify the process two application type examples are mentioned. An application example of the proposed approach to optimal block sequencing and gain distribution of 8th order cascade Butterworth filter (for two variants of OTA topologies) is given. Secondly the modeling tool is used to select the best suitable topology for a 5th order Bessel Low Pass Filter. Theoretical results are verified by comparing to transistor-level simulation withCADENCE. For the purpose of verification, the filters have also been fabricated in standard 0.5mm CMOS process. The second part of the research proposes a new linearization technique to improve the linearity of an OTA using an Active Error Feedforward technique. Most present day applications require very high linear circuits combined with low noise and low power consumption. An OTA based biquad filter has also been fabricated in 0.35mm CMOS process. The measurement results for the filter and the stand alone OTA have been discussed. The research focuses on these issues

Power Management ICs for Internet of Things, Energy Harvesting and Biomedical Devices

This dissertation focuses on the power management unit (PMU) and integrated circuits (ICs) for the internet of things (IoT), energy harvesting and biomedical devices. Three monolithic power harvesting methods are studied for different challenges of smart nodes of IoT networks. Firstly, we propose that an impedance tuning approach is implemented with a capacitor value modulation to eliminate the quiescent power consumption. Secondly, we develop a hill-climbing MPPT mechanism that reuses and processes the information of the hysteresis controller in the time-domain and is free of power hungry analog circuits. Furthermore, the typical power-performance tradeoff of the hysteresis controller is solved by a self-triggered one-shot mechanism. Thus, the output regulation achieves high-performance and yet low-power operations as low as 12 µW. Thirdly, we introduce a reconfigurable charge pump to provide the hybrid conversion ratios (CRs) as 1⅓× up to 8× for minimizing the charge redistribution loss. The reconfigurable feature also dynamically tunes to maximum power point tracking (MPPT) with the frequency modulation, resulting in a two-dimensional MPPT. Therefore, the voltage conversion efficiency (VCE) and the power conversion efficiency (PCE) are enhanced and flattened across a wide harvesting range as 0.45 to 3 V. In a conclusion, we successfully develop an energy harvesting method for the IoT smart nodes with lower cost, smaller size, higher conversion efficiency, and better applicability. For the biomedical devices, this dissertation presents a novel cost-effective automatic resonance tracking method with maximum power transfer (MPT) for piezoelectric transducers (PT). The proposed tracking method is based on a band-pass filter (BPF) oscillator, exploiting the PT’s intrinsic resonance point through a sensing bridge. It guarantees automatic resonance tracking and maximum electrical power converted into mechanical motion regardless of process variations and environmental interferences. Thus, the proposed BPF oscillator-based scheme was designed for an ultrasonic vessel sealing and dissecting (UVSD) system. The sealing and dissecting functions were verified experimentally in chicken tissue and glycerin. Furthermore, a combined sensing scheme circuit allows multiple surgical tissue debulking, vessel sealer and dissector (VSD) technologies to operate from the same sensing scheme board. Its advantage is that a single driver controller could be used for both systems simplifying the complexity and design cost. In a conclusion, we successfully develop an ultrasonic scalpel to replace the other electrosurgical counterparts and the conventional scalpels with lower cost and better functionality

High linearity analog and mixed-signal integrated circuit design

Linearity is one of the most important specifications in electrical circuits.;In Chapter 1, a ladder-based transconductance networks has been adopted first time to build a low distortion analog filters for low frequency applications. This new technique eliminated the limitation of the application with the traditional passive resistors for low frequency applications. Based on the understanding of this relationship, a strategy for designing high linear analog continuous-time filters has been developed. According to our strategy, a prototype analog integrated filter has been designed and fabricated with AMI05 0.5 um standard CMOS process. Experimental results proved this technique has the ability to provide excellent linearity with very limited active area.;In Chapter 2, the relationships between the transconductance networks and major circuit specifications have been explored. The analysis reveals the trade off between the silicon area saved by the transconductance networks and the some other important specifications such as linearity, noise level and the process variations of the overall circuit. Experimental results of discrete component circuit matched very well with our analytical outcomes to predict the change of linearity and noise performance associated with different transconductance networks.;The Chapter 3 contains the analysis and mathematical proves of the optimum passive area allocations for several most popular analog active filters. Because the total area is now manageable by the technique introduced in the Chapter 1, the further reduce of the total area will be very important and useful for efficient utilizing the silicon area, especially with the today\u27s fast growing area efficiency of the highly density digital circuits. This study presents the mathematical conclusion that the minimum passive area will be achieved with the equalized resistor and capacitor.;In the Chapter 4, a well recognized and highly honored current division circuit has been studied. Although it was claimed to be inherently linear and there are over 60 published works reported with high linearity based on this technique, our study discovered that this current division circuit can achieve, if proper circuit condition being managed, very limited linearity and all the experimental verified performance actually based on more general circuit principle. Besides its limitation, however, we invented a novel current division digital to analog converter (DAC) based on this technique. Benefiting from the simple circuit structure and moderate good linearity, a prototype 8-bit DAC was designed in TSMC018 0.2 um CMOS process and the post layout simulations exhibited the good linearity with very low power consumption and extreme small active area.;As the part of study of the output stage for the current division DAC discussed in the Chapter 4, a current mirror is expected to amplify the output current to drive the low resistive load. The strategy of achieving the optimum bandwidth of the cascode current mirror with fixed total current gain is discussed in the Chapter 5.;Improving the linearity of pipeline ADC has been the hottest and hardest topic in solid-state circuit community for decade. In the Chapter 6, a comprehensive study focus on the existing calibration algorithms for pipeline ADCs is presented. The benefits and limitations of different calibration algorithms have been discussed. Based on the understanding of those reported works, a new model-based calibration is delivered. The simulation results demonstrate that the model-based algorithms are vulnerable to the model accuracy and this weakness is very hard to be removed. From there, we predict the future developments of calibration algorithms that can break the linearity limitations for pipelined ADC. (Abstract shortened by UMI.

A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.A fully-integrated reconfigurable dual-band (760-960 MHz and 2.4-2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PA's operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by x3.24 and x1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by x2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.Peer reviewe

Design of a Direct-Modulation Transmitter with Self-Optimizing Feedback and a Highly Linear, Highly Reconfigurable, Continuously-Tunable Active-RC Baseband Filter for Multiple Standards

This work consists of two main parts: i) Design and implementation of a compact current-reusing 2.4GHz direct-modulation transmitter with on-chip automatic tuning; ii) Design and implementation of a novel highly-reconfigurable, continuously tunable, power-adjustable Active-RC filter for multiple standards. The design, analysis, and experimental verification of a proposed self-calibrating, current reused 2.4GHz, direct-modulation transmitter are introduced. A stacked arrangement of the power amplifier/voltage-controlled oscillator is presented along with a novel LC-tank-tuning algorithm with a simple, low-cost, on-chip implementation. To transmit maximum power, the tuning loop ensures the PA's resonant tank is centered around the operating frequency, and the loop requires no ADC, DSP, or external signal generator. This work also details the proposed tuning-loop algorithm and examines the frequency-dependent nonlinear power-detector. The system was implemented in TSMC 0.18[mu]m CMOS, occupies 0.7 mm² (TX) + 0.1 mm² (self tuning), and was measured in a QFN48 package on FR4 PCB. Automatically adjusting the tank-tuning bits within their tuning range results in >4dB increase in output power. With the self-tuning circuit active, the transmitter delivers a measured output power of > 0dBm to a 100-[omega] differential load, and the system consumes 22.9 mA from a 2.2-V supply. A biquad design methodology and a baseband low-pass filter is presented for wireless and wireline applications with reconfigurable frequency response, selectable order (1st/3rd/5th), continuously tunable cutoff frequency (1MHz-20MHz) and adjustable power consumption (3mW-7.5mW). A discrete capacitor array coarsely tunes the low-pass filter, and a novel Continuous Impedance Multiplier (CIM) then finely tunes the filter. Resistive/capacitive networks select between the Chebyshev and Inverse Chebyshev approximation types. Also, a new stability metric for biquads, Minimum Acceptable Phase Margin (MAPM), is presented and discussed in the context of filter compensation and passband ripple considerations. Experimental results yield an IIP3 of 31.3dBm, a THD of -40dB at 447mV[subscript pk, diff] input signal amplitude, and a DR of 71.4dB. The filters tunable range covers frequencies from 1MHz to 20MHz. In Inverse Chebyshev mode, the filter achieves a passband group delay variation less than ±2:5%. The design is fabricated in 0.13[mu]m CMOS, occupies 1.53mm², and operates from a 1-V supply

Biomimetic cochlea filters : from modelling, design to analogue VLSI implementation

This thesis presents a novel biomimetic cochlea filter which closely resembles the biological cochlea behaviour. The filter is highly feasible for analogue very-large-scale integration (VLSI) circuits, which leads to a micro-watt-power and millimetre-sized hardware implementation. By virtue of such features, the presented filter contributes to a solid foundation for future biologically-inspired audio signal processors. Unlike existing works, the presented filter is developed by taking direct inspirations from the physiologically measured results of the biological cochlea. Since the biological cochlea has prominently different characteristics of frequency response from low to high frequencies, the biomimetic cochlea filter is built by cascading three sub-filters accordingly: a 2nd-order bandpass filter for the constant gentle low-frequency response, a 2nd-order tunable low-pass filter for the variable and selective centre frequency response and a 5th-order elliptic filter for the ultra-steep roll-off at stop-band. As a proof of concept, a biomimetic cochlea filter bank is built to process audio signals, which demonstrates the highly discriminative spectral decomposition and high-resolution time-frequency analysis capabilities similar to the biological cochlea. The filter has simple representation in the Laplace domain which leads to a convenient analogue circuit realisation. A floating-active-inductor circuit cell is developed to build the corresponding RLC ladder for each of the three sub-filters. The circuits are designed based on complementary metal-oxide-semiconductor (CMOS) transistors for VLSI implementation. Non-ideal factors of CMOS transistors including parasitics, noise and mismatches are extensively analysed and consciously considered in the circuit design. An analogue VLSI chip is successfully fabricated using 0.35μ m CMOS process. The chip measurements demonstrate that the centre frequency response of the filter has about 20 dB wide gain tuning range and a high quality factor reaching maximally over 19. The filter has a 20 dB/decade constant gentle low-frequency tail and an over 300 dB/decade sharp stop-band roll-off slope. The measured results agree with the filter model expectations and are comparable with the biological cochlea characteristics. Each filter channel consumes as low as 59.5 ~90μ Wpower and occupies only 0.9 mm2 area. Besides, the biomimetic cochlea filter chip is characterised from a wide range of angles and the experimental results cover not only the auditory filter specifications but also the integrated circuit design considerations. Furthermore, following the progressive development of the acoustic resonator based on microelectro- mechanical systems (MEMS) technology, a MEMS-CMOS implementation of the proposed filter becomes possible in the future. A key challenge for such implementation is the low sensing capacitance of the MEMS resonator which suffers significantly from sensitivity degradation due to the parasitic capacitance. A novel MEMS capacitive interface circuit chip is additionally developed to solve this issue. As shown in the chip results, the interface circuit is able to cancel the parasitic capacitance and increase the sensitivity of capacitive sensors by 35 dB without consuming any extra power. Besides, the chopper-stabilisation technique is employed which effectively reduces the circuit flicker noise and offsets. Due to these features, the interface circuit chip is capable of converting a 7.5 fF capacitance change of a 1-Volt-biased 0.5 pF capacitive sensor pair into a 0.745 V signal-conditioned output while consuming only 165.2μ W power

Wide-bandwidth, high-resolution delta-sigma analog-to-digital converters

There is a significant need in recent mobile communication and wireless broadband systems for high-performance analog-to-digital converters (ADCs) that have wide bandwidth (BW>5-MHz) and high data rate (>100-Mbps). A delta-sigma ADC is recognized as a power-efficient ADC architecture when high resolution (>12-b) is required. This is due to several advantages of the delta-sigma ADC including relaxed anti-aliasing filter requirements, high signal-to-noise and distortion ratio (SNDR) and most importantly, reduced sensitivity to analog imperfections. In this thesis, several structures and design techniques are developed for the implementation of continuoustime (CT) and discrete-time (DT) delta-sigma ADCs. These techniques save the total power consumption, reduce the design complexity, and decrease the chip die area of delta-sigma modulators. First a 4th-order single stage CT delta-sigma ADC with a novel single-amplifier-biquad (SAB) based loop filter is presented. By utilizing the SAB networks in the loop filter of an Nth-order CT delta-sigma modulator, it requires only half the number of active amplifiers and feed-forward branches used in the conventional modulator architecture, thus decreasing the power consumption and area by reducing the number of amplifiers. The proposed scheme also enables the modulator to use a switch-capacitor (SC) adder due to the reduced number of feedforward branches to its summing block. As a sequence, it consumes less power compared to a conventional CT adder. With a 130-nm CMOS technology, the fabricated prototype IC achieves a dynamic range of 80 dB with 10 MHz signal bandwidth and analog power dissipation lower than 12 mW. Presented as the second scheme to save power consumption and chip die area in ΔΣ modulators is a new stage-sharing technique in a discrete-time 2-2 MASH ΔΣ ADC. The proposed technique shares all the active blocks of the modulator second stage with its first stage during the two non-overlapping clock phases. Measurement results show that the modulator designed in a 0.13-um CMOS technology achieves 76 dB SNDR over a 10 MHz conversion bandwidth dissipating less than 9 mW analog power