NP domino logic gates for Ultra Low Voltage and High Speed applications

In this thesis we present different configurations of digital circuits exploiting Ultra Low Voltage (ULV) NP domino logic style. The proposed logic style is utilized with the help of Floating gate transistors. The proposed NP domino logic gates are aimed to perform high speed operations in Ultra Low Voltage applications. The presented circuits may operate near the sub-threshold regime where the supply voltage is near the threshold voltage of the transistors. In terms of frequency, speed, robustness, Power Delay Product (PDP) and Energy Delay Product (EDP), the proposed ULV NP domino logic gates may offer significant improvement compared to the conventional CMOS logic gates. Different implementations of NOT, NAND and NOR gates are presented using both conventional and Pass Transistor Logic styles. Further, NAND and NOR gates are used to employ different configurations of Carry gates which is a speed limited factor in many arithmetic operations. These ULV NP domino Carry gates are simulated at different supply voltages in the range of 100mV to 400mV, and the performance results are presented with respect to delay, power, PDP and EDP. The proposed ULV NP domino Carry gates are cascaded together to perform addition in a 32-bit chain. The circuits are operated with respect to worst case scenario where the carry signal propagates through the whole chain. Multi-threshold (MTCMOS) and Variable-threshold (VTCMOS) techniques are employed in the ULV domino 32-bit carry chain in order to reduce the power consumption, meanwhile offering superb speed performance. Although the 32-bit carry chain offers a great advantage of speed improvement in the worst case scenario, the chain also introduces the drawback of enormous power consumption in the idle mode. The work in this thesis has resulted in three papers. Two of these papers represent various configurations of 1-bit ULV NP domino Carry gates, while the third paper examines the performance of one of the proposed ULV NP domino Carry gates in a 32-bit chain. The simulation results presented in this thesis are obtained using a 90nm TSMC CMOS process

Combined Integer and Floating Point Multiplication Architecture(CIFM) for FPGAs and Its Reversible Logic Implementation

In this paper, the authors propose the idea of a combined integer and floating point multiplier(CIFM) for FPGAs. The authors propose the replacement of existing 18x18 dedicated multipliers in FPGAs with dedicated 24x24 multipliers designed with small 4x4 bit multipliers. It is also proposed that for every dedicated 24x24 bit multiplier block designed with 4x4 bit multipliers, four redundant 4x4 multiplier should be provided to enforce the feature of self repairability (to recover from the faults). In the proposed CIFM reconfigurability at run time is also provided resulting in low power. The major source of motivation for providing the dedicated 24x24 bit multiplier stems from the fact that single precision floating point multiplier requires 24x24 bit integer multiplier for mantissa multiplication. A reconfigurable, self-repairable 24x24 bit multiplier (implemented with 4x4 bit multiply modules) will ideally suit this purpose, making FPGAs more suitable for integer as well floating point operations. A dedicated 4x4 bit multiplier is also proposed in this paper. Moreover, in the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. It is not possible to realize quantum computing without reversible logic. Thus, this paper also paper provides the reversible logic implementation of the proposed CIFM. The reversible CIFM designed and proposed here will form the basis of the completely reversible FPGAs.Comment: Published in the proceedings of the The 49th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2006), Puerto Rico, August 2006. Nominated for the Student Paper Award(12 papers are nominated for Student paper Award among all submissions

CMOS array design automation techniques

A low cost, quick turnaround technique for generating custom metal oxide semiconductor arrays using the standard cell approach was developed, implemented, tested and validated. Basic cell design topology and guidelines are defined based on an extensive analysis that includes circuit, layout, process, array topology and required performance considerations particularly high circuit speed

Research in the effective implementation of guidance computers with large scale arrays Interim report

Functional logic character implementation in breadboard design of NASA modular compute

Ianus: an Adpative FPGA Computer

Dedicated machines designed for specific computational algorithms can outperform conventional computers by several orders of magnitude. In this note we describe {\it Ianus}, a new generation FPGA based machine and its basic features: hardware integration and wide reprogrammability. Our goal is to build a machine that can fully exploit the performance potential of new generation FPGA devices. We also plan a software platform which simplifies its programming, in order to extend its intended range of application to a wide class of interesting and computationally demanding problems. The decision to develop a dedicated processor is a complex one, involving careful assessment of its performance lead, during its expected lifetime, over traditional computers, taking into account their performance increase, as predicted by Moore's law. We discuss this point in detail