An FPGA-based 3D backprojector

Subject of this thesis is the hardware architecture for the X-ray Computer Tomography. The main aim of the work is the development of a scalable, high-performance hardware for the reconstruction of a volume from cone-beam projections. A modified Feldkamp cone-beam reconstruction algorithm (Cylindrical algorithm) was used. The modifications of the original algorithm: parallelization and pipelining of the reconstruction, were formalized. Special attention was paid to the architecture of the memory system and to the schedule of the memory accesses.The developed architecture contains all steps of the reconstruction from cone-beam projections: filtering of the detector data, weighted backprojection and on-line geometry computations. The architecture was evaluated for the Xilinx Field Programmable Gate Array (FPGA). The simulations showed that the speed-up of the reconstruction of a volume is about an order of a magnitude compared to the currently available PC implementations.Gegenstand dieser Dissertation ist die Hardware-Architektur für die Röntgen-Computertomographie. Das Hauptziel der Arbeit ist die Entwicklung einer skalierbaren, leistungsstarken Hardware für die Rekonstruktion des Objektvolumens bei der Kegelstrahlprojektion. Dazu wurde ein modifizierter Feldkamp-Kegelstrahl-Rekonstruktionsalgorithmus benutzt (Zylinder-Algorithmus). Die Abwandlungen des Original-Algorithmus, Parallelisierung und Pipelining der Rekonstruktion, werden formal beschrieben. Besonderes Augenmerk wurde auf die Architektur des Speichersystems und das Timing des Speicherzugriffes gelegt. Die entwickelte Architektur enthält alle Schritte der Rekonstruktion von Kegelstrahlprojektionen: die Filterung der Detektordaten, die gewichtete Rückprojektion und Echtzeit-Geometrieberechnungen. Die Architektur wurde für ein Field Programmable Gate Array (FPGA) der Firma Xilinx evaluiert. Die Simulationen zeigten, dass die zur Rekonstruktion des Objektvolumens benötigte Zeit im Vergleich zu konventionellen PC-Implementierungen um eine Größenordnung verkürzt wurde

An FPGA-based 3D backprojector

Subject of this thesis is the hardware architecture for the X-ray Computer Tomography. The main aim of the work is the development of a scalable, high-performance hardware for the reconstruction of a volume from cone-beam projections. A modified Feldkamp cone-beam reconstruction algorithm (Cylindrical algorithm) was used. The modifications of the original algorithm: parallelization and pipelining of the reconstruction, were formalized. Special attention was paid to the architecture of the memory system and to the schedule of the memory accesses.The developed architecture contains all steps of the reconstruction from cone-beam projections: filtering of the detector data, weighted backprojection and on-line geometry computations. The architecture was evaluated for the Xilinx Field Programmable Gate Array (FPGA). The simulations showed that the speed-up of the reconstruction of a volume is about an order of a magnitude compared to the currently available PC implementations.Gegenstand dieser Dissertation ist die Hardware-Architektur für die Röntgen-Computertomographie. Das Hauptziel der Arbeit ist die Entwicklung einer skalierbaren, leistungsstarken Hardware für die Rekonstruktion des Objektvolumens bei der Kegelstrahlprojektion. Dazu wurde ein modifizierter Feldkamp-Kegelstrahl-Rekonstruktionsalgorithmus benutzt (Zylinder-Algorithmus). Die Abwandlungen des Original-Algorithmus, Parallelisierung und Pipelining der Rekonstruktion, werden formal beschrieben. Besonderes Augenmerk wurde auf die Architektur des Speichersystems und das Timing des Speicherzugriffes gelegt. Die entwickelte Architektur enthält alle Schritte der Rekonstruktion von Kegelstrahlprojektionen: die Filterung der Detektordaten, die gewichtete Rückprojektion und Echtzeit-Geometrieberechnungen. Die Architektur wurde für ein Field Programmable Gate Array (FPGA) der Firma Xilinx evaluiert. Die Simulationen zeigten, dass die zur Rekonstruktion des Objektvolumens benötigte Zeit im Vergleich zu konventionellen PC-Implementierungen um eine Größenordnung verkürzt wurde

Hardware acceleration of the trace transform for vision applications

Computer Vision is a rapidly developing field in which machines process visual data to extract meaningful information. Digitised images in their pixels and bits serve no purpose of their own. It is only by interpreting the data, and extracting higher level information that a scene can be understood. The algorithms that enable this process are often complex, and data-intensive, limiting the processing rate when implemented in software. Hardware-accelerated implementations provide a significant performance boost that can enable real- time processing. The Trace Transform is a newly proposed algorithm that has been proven effective in image categorisation and recognition tasks. It is flexibly defined allowing the mathematical details to be tailored to the target application. However, it is highly computationally intensive, which limits its applications. Modern heterogeneous FPGAs provide an ideal platform for accelerating the Trace transform for real-time performance, while also allowing an element of flexibility, which highly suits the generality of the Trace transform. This thesis details the implementation of an extensible Trace transform architecture for vision applications, before extending this architecture to a full flexible platform suited to the exploration of Trace transform applications. As part of the work presented, a general set of architectures for large-windowed median and weighted median filters are presented as required for a number of Trace transform implementations. Finally an acceleration of Pseudo 2-Dimensional Hidden Markov Model decoding, usable in a person detection system, is presented. Such a system can be used to extract frames of interest from a video sequence, to be subsequently processed by the Trace transform. All these architectures emphasise the need for considered, platform-driven design in achieving maximum performance through hardware acceleration

GSI Scientific Report 2009 [GSI Report 2010-1]

Displacement design response spectrum is an essential component for the currently-developing displacement-based seismic design and assessment procedures. This paper proposes a new and simple method for constructing displacement design response spectra on soft soil sites. The method takes into account modifications of the seismic waves by the soil layers, giving due considerations to factors such as the level of bedrock shaking, material non-linearity, seismic impedance contrast at the interface between soil and bedrock, and plasticity of the soil layers. The model is particularly suited to applications in regions with a paucity of recorded strong ground motion data, from which empirical models cannot be reliably developed