Design and improvement a high speed and low power 8/9 frequency divider with TSPC dynamic logic

A low power and high speed 8/9 CMOS programmable dynamic frequency divider has been designed. It contains a control bit by which can obtain 1/9 and 1/8 input frequency in output. In spite of the variations in size and structure of circuit, the 53% improvement in power dissipation has been achieved. Power dissipation about 1.6 mw in a 2.78 GHz Frequency Rate, 2.5 volt power supply circuit is verified by HSPISE simulatio

A fully integrated multiband frequency synthesizer for WLAN and WiMAX applications

This paper presents a fractional N frequency synthesizer which covers WLAN and WiMAX frequencies on a single chip. The synthesizer is fully integrated in 0.35μm BiCMOS AMS technology except crystal oscillator. The synthesizer operates at four frequency bands (3.101-3.352GHz, 3.379-3.727GHz, 3.7-4.2GHz, 4.5-5.321GHz) to provide the specifications of 802.16 and 802.11 a/b/g/y. A single on-chip LC - Gm based VCO is implemented as the core of this synthesizer. Different frequency bands are selected via capacitance switching and fine tuning is done using varactor for each of these bands. A bandgap reference circuit is implemented inside of this charge pump block to generate temperature and power supply independent reference currents. Simulated settling time is around 10μsec. Total power consumption is measured to be 118.6mW without pad driving output buffers from a 3.3V supply. The phase noise of the oscillator is lower than -116.4dbc/Hz for all bands. The circuit occupies 2.784 mm2 on Si substrate, including DC, Digital and RF pads

Design and layout strategies for integrated frequency synthesizers with high spectral purity

Dieser Beitrag ist mit Zustimmung des Rechteinhabers aufgrund einer (DFG geförderten) Allianz- bzw. Nationallizenz frei zugänglich.This publication is with permission of the rights owner freely accessible due to an Alliance licence and a national licence (funded by the DFG, German Research Foundation) respectively.Design guidelines for fractional-N phase-locked loops with a high spectral purity of the output signal are presented. Various causes for phase noise and spurious tones (spurs) in integer-N and fractional-N phase-locked loops (PLLs) are briefly described. These mechanisms include device noise, quantization noise folding, and noise coupling from charge pump (CP) and reference input buffer to the voltage-controlled oscillator (VCO) and vice versa through substrate and bondwires. Remedies are derived to mitigate the problems by using proper PLL parameters and a careful chip layout. They include a large CP current, sufficiently large transistors in the reference input buffer, linearization of the phase detector, a high speed of the programmable frequency divider, and minimization of the cross-coupling between the VCO and the other building blocks. Examples are given based on experimental PLLs in SiGe BiCMOS technologies for space communication and wireless base stations.BMBF, 03ZZ0512A, Zwanzig20 - Verbundvorhaben: fast-spot; TP1: Modularer Basisband- Prozessor mit extrem hohen Datenraten, sehr kurzen Latenzzeiten und SiGe-Analog-Frontend-IC-Fertigung bei >200 GHz Trägerfrequen

Architectures for RF Frequency synthesizers

Frequency synthesizers are an essential building block of RF communication products. They can be found in traditional consumer products, in personal communication systems, and in optical communication equipment. Since frequency synthesizers are used in many different applications, different performance aspects may need to be considered in each case. The main body of the text describes a conceptual framework for analyzing the performance of PLL frequency synthesizers, and presents optimization procedures for the different performance aspects. The analysis of the PLL properties is performed with the use of the open-loop bandwidth and phase margin concepts, to enable the influence of higher-order poles to be taken into account from the beginning of the design process. The theoretical system analysis is complemented by descriptions of innovative system and building block architectures, by circuit implementations in bipolar and CMOS technologies, and by measurement results. Architectures for RF Frequency Synthesizers contains basic information for the beginner as well as in-depth knowledge for the experienced designer. It is widely illustrated with practical design examples used in industrial products.\ud Written for:\ud Electrical and electronic engineer

Automatic oscillator frequency control system

A frequency control system makes an initial correction of the frequency of its own timing circuit after comparison against a frequency of known accuracy and then sequentially checks and corrects the frequencies of several voltage controlled local oscillator circuits. The timing circuit initiates the machine cycles of a central processing unit which applies a frequency index to an input register in a modulo-sum frequency divider stage and enables a multiplexer to clock an accumulator register in the divider stage with a cyclical signal derived from the oscillator circuit being checked. Upon expiration of the interval, the processing unit compares the remainder held as the contents of the accumulator against a stored zero error constant and applies an appropriate correction word to a correction stage to shift the frequency of the oscillator being checked. A signal from the accumulator register may be used to drive a phase plane ROM and, with periodic shifts in the applied frequency index, to provide frequency shift keying of the resultant output signal. Interposition of a phase adder between the accumulator register and phase plane ROM permits phase shift keying of the output signal by periodic variation in the value of a phase index applied to one input of the phase adder

Temperature sensitive oscillator

An oscillator circuit for sensing and indicating temperature by changing oscillator frequency with temperature comprises a programmable operational amplifier which is operated on the roll-off portion of its gain versus frequency curve and has its output directly connected to the inverting input to place the amplifier in a follower configuration. Its output is also connected to the non-inverting input by a capacitor with a crystal or other tuned circuit also being connected to the non-inverting input. A resistor is connected to the program input of the amplifier to produce a given set current at a given temperature, the set current varying with temperature. As the set current changes, the gain-bandwidth of the amplifier changes and, in turn, the reflected capacitance across the crystal changes, thereby providing the desired change in oscillator frequency by pulling the crystal. There is no requirement that a crystal employed with this circuit display either a linear frequency change with temperature or a substantial frequency change with temperature

Fully Integrated Frequency and Phase Generation for a 6-18GHz Tunable Multi-Band Phased-Array Receiver in CMOS

Fully integrated frequency-phase generators for a 6-18GHz wide-band phased-array receiver element are presented that generate 5-7GHz and 9-12GHz first LO signals with less than -95dBc/Hz phase noise at 100kHz offset. Second LO signals with digitally controllable fourquadrant phase- and amplitude spread with better than 3° resolution are generated and allow removal of systematic reference clock skew as well as accurate selection of the received signal phase. This frequency- and phase generation scheme was successfully demonstrated in a 6-18GHz receiver system configured as an electrical 4-element array