Investigation of FACTS devices to improve power quality in distribution networks

Flexible AC transmission system (FACTS) technologies are power electronic solutions that improve power transmission through enhanced power transfer volume and stability, and resolve quality and reliability issues in distribution networks carrying sensitive equipment and non-linear loads. The use of FACTS in distribution systems is still in its infancy. Voltages and power ratings in distribution networks are at a level where realistic FACTS devices can be deployed. Efficient power converters and therefore loss minimisation are crucial prerequisites for deployment of FACTS devices. This thesis investigates high power semiconductor device losses in detail. Analytical closed form equations are developed for conduction loss in power devices as a function of device ratings and operating conditions. These formulae have been shown to predict losses very accurately, in line with manufacturer data. The developed formulae enable circuit designers to quickly estimate circuit losses and determine the sensitivity of those losses to device voltage and current ratings, and thus select the optimal semiconductor device for a specific application. It is shown that in the case of majority carrier devices (such as power MOSFETs), the conduction power loss (at rated current) increases linearly in relation to the varying rated current (at constant blocking voltage), but is a square root of the variable blocking voltage when rated current is fixed. For minority carrier devices (such as a pin diode or IGBT), a similar relationship is observed for varying current, however where the blocking voltage is altered, power losses are derived as a square root with an offset (from the origin). Finally, this thesis conducts a power loss-oriented evaluation of cascade type multilevel converters suited to reactive power compensation in 11kV and 33kV systems. The cascade cell converter is constructed from a series arrangement of cell modules. Two prospective structures of cascade type converters were compared as a case study: the traditional type which uses equal-sized cells in its chain, and a second with a ternary relationship between its dc-link voltages. Modelling (at 81 and 27 levels) was carried out under steady state conditions, with simplified models based on the switching function and using standard circuit simulators. A detailed survey of non punch through (NPT) and punch through (PT) IGBTs was completed for the purpose of designing the two cascaded converters. Results show that conduction losses are dominant in both types of converters in NPT and PT IGBTs for 11kV and 33kV systems. The equal-sized converter is only likely to be useful in one case (27-levels in the 33kV system). The ternary-sequence converter produces lower losses in all other cases, and this is especially noticeable for the 81-level converter operating in an 11kV network

Optimisation of High Reliability Integrated Motor Drives

The development of integrated motor drives (IMDs) with high volumetric power density and reliability are crucial for the continued development and adoption of electric vehicles (EV). The development of the wide bandgap (WBG) devices, especially Silicon Carbide (SiC) MOSFETs, enables new possibilities for traction drive systems. However, to maximise the benefits of SiC, the IMD design process, including passive component selection, control and thermal management should be optimised. This thesis goes through the initial major design steps in SiC power system design, from SiC device analysis and modelling to circuit design and electrothermal simulation of an IMD system. A novel approach to discrete SiC MOSFET selection, using a method of calculating performance based on experimental data, is described. Dynamic behaviour of a family of 1200 V MOSFETs is studied at temperatures up to 175 °C using a double pulse test to show the combined effect of the differences in internal design between MOSFETs with different current ratings. It is observed that the 30 mΩ MOSFET had a 24 % higher switching loss than a 140 mΩ at a 30 A load current. The study then goes on to compare the effect of switching frequency, paralleling of MOSFETs and the device type used to demonstrate the inverter design with the lowest power losses, which will equate to low temperatures and high lifetime. The novel methodology can find the optimal choice of MOSFET from the family, and number required through paralleling, for a circuit when given the load current, temperature and switching. Understanding the device interdependencies in a single family is utilised to also predict the relative performance between SiC MOSFETs from different manufacturers. An axial-flux permanent magnet synchronous motor (PMSM) driven by a three-phase SiC inverter is simulated in PLECS using experimentally validated MOSFET models chosen by the device selection methodology. Electrothermal analysis shows the influence of switching frequency, temperature, MOSFETs paralleling and DC-link capacitance on voltage ripple, total harmonic distortion, efficiency and MOSFET loss and temperature profiles. With a 60 % decrease in THD and 50 % increase in maximum MOSFET junction temperature when switching frequency is increased from 10 to 100 kHz. The high-temperature stress on the semiconductors due to close proximity with the ma- chine stator means reliability is an important consideration that is yet to be fully investigated in IMD optimisations. This study uses a lifetime model specific to the transistor package TO-247 in reliability optimisation for IMD for the first time. It requires detailed MOSFET simulation outputs to provide a highly accurate lifetime for discrete SiC MOSFETs. Both single and multi-objective optimisations of the volume and lifetime of the three- phase inverter are presented. The single objective optimisation demonstrates the minimum volume and the corresponding switching frequency and lifetime when between three and six MOSFETs are paralleled at a temperature range between 50 and 150 °C. Design constraints were set limiting the feasible switching frequency range to between 13 kHz because of THD and 118 kHz because of efficiency limits, corresponding to required DC-link capacitors of 520 and 55 μF respectively. Increases in temperature were found to further limit the maximum switching frequency and therefore increase the minimum volume of the inverter. A Pareto front identifies a range of possible solutions for the volume and lifetime of an inverter with six paralleled MOSFETs through the multi-objective objective procedure. Further analysis of these possible solutions identified a single optimal solution for the system, using a DC-link capacitance of 190 μF at 45 kHz, giving a combined volume of the capacitor and MOSFETs of 440 cm3 and a lifetime of 12,000 hours. Finally, the electrothermal analysis of a dual inverter driving a symmetric six-phase PMSM is presented with the benefits of modular multi-phase systems in IMDs summarised. Effect on performance of lower per-phase current, interleaving strategies and fault tolerance are analysed and compared to equivalent three-phase systems, for 60 kW and 120 kW operation. A novel method for lifetime prediction of systems with paralleled MOSFETs or fault tolerance capabilities considering incremental damage is developed based on TO-247 lifetime calculations from PLECS simulation, and component-level reliability profiles using Monte Carlo analysis. The dual inverter is used to model the system and implements control schemes for both single-phase and single inverter failure while maintaining the 4000 rpm and 140 Nm speed and torque requirements. A twofold increase in B10 lifetime of is observed when the effect of paralleled SiC MOSFETs prevents immediate system failure in a three-phase inverter. A computational fluid dynamics (CFD) and 3D finite element thermal model are designed to study the inverter behaviour based on the thermal analysis of its shared cooling plate with a 300 mm diameter axial flux PMSM. Concentric layout designs minimise the variation of junction temperatures to 5 °C and the effect of the flow rate and temperature of the coolant in the PMSM cold plate is presented between 5 and 30 l/min. The multi-objective optimisation procedure used to compare the dual inverter demonstrated it outperformed the three-phase inverter with 15 % smaller required DC-link capacitance, higher efficiency and increased lifetime in part due to its fault-tolerant nature. The optimal dual inverter considering the design constraints consists of four 40 μF KEMET film capacitors operating with a switching frequency of 46 kHz giving an inverter volume of 300 cm3 and a lifetime of 16.3 years, assuming 1000 hours of operation annually

New Processes and Technologies to Reduce the Low‐Frequency Noise of Digital and Analog Circuits

The chapter is intended to provide the reader with means to reduce low‐frequency noise in Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET). It is demonstrated that low‐resistivity source and drain electrodes can greatly lower the low‐frequency noise level by suppressing their contribution to the total noise. Furthermore, new plasma processes having the advantages to work at low electron temperature can achieve a further reduction, thanks to the fabrication of a better gate oxide and to a reduction of damages generally induced by conventional plasma processes. Reducing the impact of the traps on the carrier flowing inside the channel by burying the channel can also achieve a reduction of the noise level, but unfortunately at the cost of a degradation of the electrical performances. Finally, the noise analysis of the low‐frequency noise in accumulation‐mode MOSFETs showed that these newly developed devices have a lower noise level than conventional structures, which, in addition to their superiority in term of electrical performances, establishes them as a serious platform for the next Complementary Metal-Oxide-Semiconductor Field-Effect-Transistor (CMOS) technology

Impact of BTI induced threshold voltage shifts in shoot-through currents from crosstalk in SiC MOSFETs

In this paper a method for evaluating the implications of threshold voltage (VTH) drift from gate voltage stress in SiC MOSFETs is presented. By exploiting the Miller coupling between two devices in the same phase leg, the technique uses the shoot-through charge from parasitic turn-ON to characterize the impact of Bias Temperature Instability (BTI) induced VTH shift. Traditional methods of BTI characterization rely on the application of a stress voltage without characterizing the implication of the VTH shift on the switching characteristics of the device in a circuit. Unlike conventional methods, this method uses the actual converter environment to investigate the implications of VTH shift and should therefore be of more interest to applications engineers as opposed to device physicists. Furthermore, a common problem is the underestimation of the VTH shift since recovery from charge de-trapping can mask the true extent of the problem. The impact of temperature, the recovery time after stress removal and polarity of the stress have been studied for a set of commercially available SiC MOSFETs

Deep Learning Algorithm for Advanced Level-3 Inverse-Modeling of Silicon-Carbide Power MOSFET Devices

Inverse modelling with deep learning algorithms involves training deep architecture to predict device's parameters from its static behaviour. Inverse device modelling is suitable to reconstruct drifted physical parameters of devices temporally degraded or to retrieve physical configuration. There are many variables that can influence the performance of an inverse modelling method. In this work the authors propose a deep learning method trained for retrieving physical parameters of Level-3 model of Power Silicon-Carbide MOSFET (SiC Power MOS). The SiC devices are used in applications where classical silicon devices failed due to high-temperature or high switching capability. The key application of SiC power devices is in the automotive field (i.e. in the field of electrical vehicles). Due to physiological degradation or high-stressing environment, SiC Power MOS shows a significant drift of physical parameters which can be monitored by using inverse modelling. The aim of this work is to provide a possible deep learning-based solution for retrieving physical parameters of the SiC Power MOSFET. Preliminary results based on the retrieving of channel length of the device are reported. Channel length of power MOSFET is a key parameter involved in the static and dynamic behaviour of the device. The experimental results reported in this work confirmed the effectiveness of a multi-layer perceptron designed to retrieve this parameter.Comment: 13 pages, 8 figures, to be published on Journal of Physics: Conference Serie

Hierarchical approach to 'atomistic' 3-D MOSFET simulation

We present a hierarchical approach to the 'atomistic' simulation of aggressively scaled sub-0.1-μm MOSFETs. These devices are so small that their characteristics depend on the precise location of dopant atoms within them, not just on their average density. A full-scale three-dimensional drift-diffusion atomistic simulation approach is first described and used to verify more economical, but restricted, options. To reduce processor time and memory requirements at high drain voltage, we have developed a self-consistent option based on a solution of the current continuity equation restricted to a thin slab of the channel. This is coupled to the solution of the Poisson equation in the whole simulation domain in the Gummel iteration cycles. The accuracy of this approach is investigated in comparison to the full self-consistent solution. At low drain voltage, a single solution of the nonlinear Poisson equation is sufficient to extract the current with satisfactory accuracy. In this case, the current is calculated by solving the current continuity equation in a drift approximation only, also in a thin slab containing the MOSFET channel. The regions of applicability for the different components of this hierarchical approach are illustrated in example simulations covering the random dopant-induced threshold voltage fluctuations, threshold voltage lowering, threshold voltage asymmetry, and drain current fluctuations

Simulation study of scaling design, performance characterization, statistical variability and reliability of decananometer MOSFETs

This thesis describes a comprehensive, simulation based scaling study – including device design, performance characterization, and the impact of statistical variability – on deca-nanometer bulk MOSFETs. After careful calibration of fabrication processes and electrical characteristics for n- and p-MOSFETs with 35 nm physical gate length, 1 nm EOT and stress engineering, the simulated devices closely match the performance of contemporary 45 nm CMOS technologies. Scaling to 25 nm, 18 nm and 13 nm gate length n and p devices follows generalized scaling rules, augmented by physically realistic constraints and the introduction of high-k/metal-gate stacks. The scaled devices attain the performance stipulated by the ITRS. Device a.c. performance is analyzed, at device and circuit level. Extrinsic parasitics become critical to nano-CMOS device performance. The thesis describes device capacitance components, analyzes the CMOS inverter, and obtains new insights into the inverter propagation delay in nano-CMOS. The projection of a.c. performance of scaled devices is obtained. The statistical variability of electrical characteristics, due to intrinsic parameter fluctuation sources, in contemporary and scaled decananometer MOSFETs is systematically investigated for the first time. The statistical variability sources: random discrete dopants, gate line edge roughness and poly-silicon granularity are simulated, in combination, in an ensemble of microscopically different devices. An increasing trend in the standard deviation of the threshold voltage as a function of scaling is observed. The introduction of high-k/metal gates improves electrostatic integrity and slows this trend. Statistical evaluations of variability in Ion and Ioff as a function of scaling are also performed. For the first time, the impact of strain on statistical variability is studied. Gate line edge roughness results in areas of local channel shortening, accompanied by locally increased strain, both effects increasing the local current. Variations are observed in both the drive current, and in the drive current enhancement normally expected from the application of strain. In addition, the effects of shallow trench isolation (STI) on MOSFET performance and on its statistical variability are investigated for the first time. The inverse-narrow-width effect of STI enhances the current density adjacent to it. This leads to a local enhancement of the influence of junction shapes adjacent to the STI. There is also a statistical impact on the threshold voltage due to random STI induced traps at the silicon/oxide interface

Statistical circuit simulations - from ‘atomistic’ compact models to statistical standard cell characterisation

This thesis describes the development and application of statistical circuit simulation methodologies to analyse digital circuits subject to intrinsic parameter fluctuations. The specific nature of intrinsic parameter fluctuations are discussed, and we explain the crucial importance to the semiconductor industry of developing design tools which accurately account for their effects. Current work in the area is reviewed, and three important factors are made clear: any statistical circuit simulation methodology must be based on physically correct, predictive models of device variability; the statistical compact models describing device operation must be characterised for accurate transient analysis of circuits; analysis must be carried out on realistic circuit components. Improving on previous efforts in the field, we posit a statistical circuit simulation methodology which accounts for all three of these factors. The established 3-D Glasgow atomistic simulator is employed to predict electrical characteristics for devices aimed at digital circuit applications, with gate lengths from 35 nm to 13 nm. Using these electrical characteristics, extraction of BSIM4 compact models is carried out and their accuracy in performing transient analysis using SPICE is validated against well characterised mixed-mode TCAD simulation results for 35 nm devices. Static d.c. simulations are performed to test the methodology, and a useful analytic model to predict hard logic fault limitations on CMOS supply voltage scaling is derived as part of this work. Using our toolset, the effect of statistical variability introduced by random discrete dopants on the dynamic behaviour of inverters is studied in detail. As devices scaled, dynamic noise margin variation of an inverter is increased and higher output load or input slew rate improves the noise margins and its variation. Intrinsic delay variation based on CV/I delay metric is also compared using ION and IEFF definitions where the best estimate is obtained when considering ION and input transition time variations. Critical delay distribution of a path is also investigated where it is shown non-Gaussian. Finally, the impact of the cell input slew rate definition on the accuracy of the inverter cell timing characterisation in NLDM format is investigated