Simulation-based verification of EM side-channel attack resilience of embedded cryptographic systems

Electromagnetic (EM) fields emanated due to switching currents in crypto-blocks can be an effective non-invasive channel for extracting secret keys. Accurate design-time simulation tools are needed to predict vulnerabilities and improve resilience of embedded systems to EM side-channel analysis attacks. Modeling such attacks is challenging, however, as it requires a multitude of expensive simulations across multiple circuit abstraction levels together with EM simulations. In this work, a simulation ow is developed to study the differential EM analysis (DEMA) attack on the Advanced Encryption System (AES) block cipher. The proposed ow enables design-time evaluation of realistic DEMA attacks for the first time. The major challenge is accurately computing signals received by a nearby probe at various positions above the chip surface for a large number of AES encryptions. This requires rapidly generating spatial distribution and transient EM radiation of on-chip current waveforms. Commercial CAD tools are used to generate space-time samples of these waveforms and a custom EM simulator to radiate them. The computations are sped up by focusing on information-leaking time windows, performing hybrid gate- and transistor-level simulations, radiating only the currents on top metallization layers, and generating traces for different encryptions in parallel. These methods reduce simulation time to a manageable ~ 20 hrs wall-clock time/attack allowing a previously impossible level of vulnerability analysis. The proposed ow also allows pinpointing critical regions on the chip most susceptible to EM attacks. We demonstrate that exploiting the spatial profile of circuit elements can reveal cryptographic keys with significantly fewer number of traces than DPA , guiding designers to the most critical areas of the layout. This enables targeted deployment of counter-measures to the highest information-leaking design componentsElectrical and Computer Engineerin

Integrated On-Silicon and On-glass Antennas for Mm-Wave Applications

The paper presents several integrated high frequency antenna prototypes based on Si/CMOS and on-glass technologies for millimeter-wave (mm-wave) applications. On-chip loop antenna and dipole radiator are presented. In addition, a wide-band dipole-patch antenna design for the range of 74 – 104 GHz is integrated into a CMOS chip with an on-chip pulse generator. In addition, an implementation of a fully on-Silicon antenna array integrated with a timed-array transmitter. To control the beam-forming of this array, a digital-based time adjustment circuit is integrated together with the antenna array. Simulated and measured data including return loss, and radiation patterns are presented. This paper also introduces an on-glass antenna prototypes fabricated on quartz substrate. The on-glass antenna is to demonstrate for handset or automobile’s windshield/windows applications where radio waves could be transmitted and received from various directions. The results show several compact antenna candidates integrated by both Silicon and quartz substrates towards mm-Wave/sub-mm-Wave sensing and communication applications

Research on performance enhancement for electromagnetic analysis and power analysis in cryptographic LSI

制度:新 ; 報告番号:甲3785号 ; 学位の種類:博士(工学) ; 授与年月日:2012/11/19 ; 早大学位記番号:新6161Waseda Universit

Passive harmonic generation at spring contacts

In the first paper, the RF passive harmonic generation phenomenon on the spring contact is studied. A spring contact harmonic generation measurement system is developed. The factors that may have an impact on the spring contact harmonic generation, such as contact material, contact force, and contact resistance are characterized by the measurement system. The gold-to-gold contact is found to be much superior to the stainless-steel contacts. It is also found that the passive nonlinearity at the spring contact is the semiconductor-like junction formed by the surface oxide film. In the second paper, we show that the maximum E-field coupling occurs at a location slightly offset from the trace center. The E-field coupling to a shielded H-field probe at such a position leads to differential mode coupling which the standard shield of an H-field probe is unable to suppress. The coupling mechanism is investigated and a differential E-field coupling suppression approach is proposed. In the third paper, a measurement system which uses acoustic vibration to locate passive intermodulation (PIM) sources in base station antennas is presented. This measurement system uses mechanical vibration to modulate the PIM signal. By introducing the acoustic vibration at different locations in the base station antenna and observing if the PIM signal is modulated by the acoustic frequency, the most likely location of the PIM source is identified --Abstract, page iv

Contactless, high resolution characterization of current and voltage waveforms within high power communication amplifiers

Characterisation of high-power communications-based amplifiers (PAs) has generated many thousands of research papers and much of this work assumes the transistors at the heart of these (PAs) to be a ‘large’ holistic entity. Given that high-power communications-based transistors are made up of multiple, parallel transistors on a single substrate, it is this intermediate scale range, within the periphery of the device, but much larger than the geometrical scale of the epitaxy and the lithography, that requires deeper investigation. Raman-based thermography may add a dimension of spatially varying heat dissipation but ‘lifting the bonnet’ of the transistor and making internal contactless measurements of current and voltage is the only way to fully account for the myriads of parasitic effects that have been observed by countless researchers. To date, however, very little research has been conducted on quantifying the individual spatial voltages within the transistor in order to fully characterise it. Miniaturised contactless current and voltage probes are theorised, designed, characterised and optimised in this thesis to deliver a robust and reliable means of transistor characterisation at these internal spatial dimensions. The contactless voltage probe presented in this work has a spatial resolution four times finer than the previously reported voltage probe, with a useful bandwidth up to 7 GHz and a controllable passive gain up to 20 dB at the desired operating frequency. The pinnacle of this thesis delivers a novel shielded contactless current probe, capable of high-resolution scanning, culminating in a ‘quasi-calibrated’ measurement of the distributed currents within a multi-finger LDMOS transistor operating at high power and high frequency. The spatial resolution of this shielded contactless current probe is 62.5 μm with 22.7 dB average rejection ratio to the electric field, and it has a broad bandwidth up to 9 GHz. To date, this type of contactless current measurement has not been reported elsewhere

Memristors

This Edited Volume Memristors - Circuits and Applications of Memristor Devices is a collection of reviewed and relevant research chapters, offering a comprehensive overview of recent developments in the field of Engineering. The book comprises single chapters authored by various researchers and edited by an expert active in the physical sciences, engineering, and technology research areas. All chapters are complete in itself but united under a common research study topic. This publication aims at providing a thorough overview of the latest research efforts by international authors on physical sciences, engineering, and technology,and open new possible research paths for further novel developments

Selection of a new hardware and software platform for railway interlocking

The interlocking system is one of the main actors for safe railway transportation. In most cases, the whole system is supplied by a single vendor. The recent regulations from the European Union direct for an “open” architecture to invite new game changers and reduce life-cycle costs. The objective of the thesis is to propose an alternative platform that could replace a legacy interlocking system. In the thesis, various commercial off-the-shelf hardware and software products are studied which could be assembled to compose an alternative interlocking platform. The platform must be open enough to adapt to any changes in the constituent elements and abide by the proposed baselines of new standardization initiatives, such as ERTMS, EULYNX, and RCA. In this thesis, a comparative study is performed between these products based on hardware capacity, architecture, communication protocols, programming tools, security, railway certifications, life-cycle issues, etc

Integrated quantum photonics

EThOS - Electronic Theses Online ServiceGBUnited Kingdo