38 research outputs found

    NetFPGA: status, uses, developments, challenges, and evaluation

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    The constant growth of the Internet, driven by the demand for timely access to data center networks; has meant that the technological platforms necessary to achieve this purpose are outside the current budgets. In this order to make and validate relevant, timely and relevant contributions; it is necessary that a wider community, access to evaluation, experimentation and demonstration environments with specifications that can be compared with existing networking solutions. This article introduces the NetFPGA, which is a platform to develop network hardware for reconfigurable and rapid prototyping. It’s introduces the application areas in high-performance networks, advantages for traffic analysis, packet flow, hardware acceleration, power consumption and parallel processing in real time. Likewise, it presents the advantages of the platform for research, education, innovation, and future trends of this platform. Finally, we present a performance evaluation of the tool called OSNT (Open-Source Network Tester) and shows that OSNT has 95% accuracy of timestamp with resolution of 10ns for the generation of TCP traffic, and 90% efficiency capturing packets at 10Gbps of full line-rate

    High precision packet time-stamping using NetFPGA 10 G plataform

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    High precision network measurements is an area with high interest as the performance of the networks a ects the quality and the cost of a service between a Network Service Provider (NSP) and the costumer. The increase of the network speed leads the measurements of the software system to be unreliable even though their low cost and the high con gurability. The solution for high network performance measurement at high network speed is hardware system that can guarantee standard high performance. The NetFPGA is an open source low-cost platform based on networks that permits to implement network system easily due to the wide reference components that o ers. The second version of the NetFPGA platform designed by the Stanford University has four 10GigE SFP+ interfaces and a powerful FPGA providing the ability to implement network system over copper and optic ber at 1Gbps and 10Gbps. This NetFPGA 10G project can measure the network parameters at high precision with the technique of the time stamping. A GPS system guarantees the high precision of the time. The dynamically generation of back-to-back packets gives the exibility for measurements without any recaptured ows that no other system provides. The save of the captured packets gives the possibility of o -line further analysis of the network.Medidas de red de alta precisión es un área de gran interés de como el desempeño de las redes afecta la calidad y el costo del servicio entre un proveedor de servicios de red (NSP) y el consumidor. El incremento de la velocidad de las redes lleva a que las mediciones por software sean poco fiables a pesar de su bajo coste y alta configurabilidad. La solución para mediciones de alto rendimiento en redes de alta velocidad son sistemas hardware que pueden garantizar alta rendimiento estándar. La NetFPGA es una plataforma de código abierto de bajo coste basado en redes que permite implementar sistemas de red con facilidad debido al gran soporte de componentes de referencia que ofrece. La segunda versión de la plataforma de NetFPGA desarrollada por la Universidad de Stanford tiene cuatro interfaces de 10GigE de tecnología SFP+ y una potente FPGA que permite implementar sistemas de red con conexiones de cobre y de fibra óptica de 1Gbps y 10Gbps. Este proyecto de NetFPGA 10G puede medir parámetros de red con alta precisión con la técnica de marca de tiempo (time-stamping). Un sistema GPS garantiza alta precisión de tiempo. La generación dinámica de paquetes consecutivos da la flexibilidad para mediciones sin reproducir tráfico anteriormente capturado, cosa que otros sistemas no pueden hacer. El guardado de paquetes generados da la posibilidad de futuros análisis sin repetir los experimentos (análisis off-line

    An outright open source approach for simple and pragmatic internet eXchange

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    L'Internet, le réseaux des réseaux, est indispensable à notre vie moderne et mondialisée et en tant que ressource publique il repose sur l'inter opérabilité et la confiance. Les logiciels libres et open source jouent un rôle majeur pour son développement. Les points d'échange Internet (IXP) où tous les opérateurs de type et de taille différents peuvent s'échanger du trafic sont essentiels en tant que lieux d'échange neutres et indépendants. Le service fondamental offert par un IXP est une fabrique de commutation de niveau 2 partagée. Aujourd'hui les IXP sont obligés d'utiliser des technologies propriétaires pour leur fabrique de commutations. Bien qu'une fabrique de commutations de niveau 2 se doit d'être une fonctionnalité de base, les solutions actuelles ne répondent pas correctement aux exigences des IXPs. Cette situation est principalement dûe au fait que les plans de contrôle et de données sont intriqués sans possibilités de programmer finement le plan de commutation. Avant toute mise en œuvre, il est primordial de tester chaque équipement afin de vérifier qu'il répond aux attentes mais les solutions de tests permettant de valider les équipements réseaux sont toutes non open source, commerciales et ne répondent pas aux besoins techniques d'indépendance et de neutralité. Le "Software Defined Networking" (SDN), nouveau paradigme découplant les plans de contrôle et de données utilise le protocole OpenFlow qui permet de programmer le plan de commutation Ethernet haute performance. Contrairement à tous les projets de recherches qui centralisent la totalité du plan de contrôle au dessus d'OpenFlow, altérant la stabilité des échanges, nous proposons d'utiliser OpenFlow pour gérer le plan de contrôle spécifique à la fabrique de commutation. L'objectif principal de cette thèse est de proposer "Umbrella", fabrique de commutation simple et pragmatique répondant à toutes les exigences des IXPs et en premier lieu à la garantie d'indépendance et de neutralité des échanges. Dans la première partie, nous présentons l'architecture "Umbrella" en détail avec l'ensemble des tests et validations démontrant la claire séparation du plan de contrôle et du plan de données pour augmenter la robustesse, la flexibilité et la fiabilité des IXPs. Pour une exigence d'autonomie des tests nécessaires pour les IXPs permettant l'examen de la mise en œuvre d'Umbrella et sa validation, nous avons développé l'"Open Source Network Tester" (OSNT), un système entièrement open source "hardware" de génération et de capture de trafic. OSNT est le socle pour l"OpenFLow Operations Per Second Turbo" (OFLOPS Turbo), la plate-forme d'évaluation de commutation OpenFlow. Le dernier chapitre présente le déploiement de l'architecture "Umbrella" en production sur un point d'échange régional. Les outils de test que nous avons développés ont été utilisés pour vérifier les équipements déployés en production. Ce point d'échange, stable depuis maintenant un an, est entièrement géré et contrôlé par une seule application Web remplaçant tous les systèmes complexes et propriétaires de gestion utilisés précédemment.In almost everything we do, we use the Internet. The Internet is indispensable for our today's lifestyle and to our globalized financial economy. The global Internet traffic is growing exponentially. IXPs are the heart of Internet. They are highly valuable for the Internet as neutral exchange places where all type and size of autonomous systems can "peer" together. The IXPs traffic explode. The 2013 global Internet traffic is equivalent with the largest european IXP today. The fundamental service offer by IXP is a shared layer2 switching fabric. Although it seems a basic functionality, today solutions never address their basic requirements properly. Today networks solutions are inflexible as proprietary closed implementation of a distributed control plane tight together with the data plane. Actual network functions are unmanageable and have no flexibility. We can understand how IXPs operators are desperate reading the EURO-IX "whishlist" of the requirements who need to be implemented in core Ethernet switching equipments. The network vendor solutions for IXPs based on MPLS are imperfect readjustment. SDN is an emerging paradigm decoupling the control and data planes, on opening high performance forwarding plane with OpenFlow. The aims of this thesis is to propose an IXP pragmatic Openflow switching fabric, addressing the critical requirements and bringing more flexibility. Transparency is better for neutrality. IXPs needs a straightforward more transparent layer2 fabric where IXP participants can exchange independently their traffic. Few SDN solutions have been presented already but all of them are proposing fuzzy layer2 and 3 separation. For a better stability not all control planes functions can be decoupled from the data plane. As other goal statement, networking testing tools are essential for qualifying networking equipment. Most of them are software based and enable to perform at high speed with accuracy. Moreover network hardware monitoring and testing being critical for computer networks, current solutions are both extremely expensive and inflexible. The experience in deploying Openflow in production networks has highlight so far significant limitations in the support of the protocol by hardware switches. We presents Umbrella, a new SDN-enabled IXP fabric architecture, that aims at strengthening the separation of control and data plane to increase both robustness, flexibility and reliability of the exchange. Umbrella abolish broadcasting with a pseudo wire and segment routing approach. We demonstrated for an IXP fabric not all the control plane can be decoupled from the date plane. We demonstrate Umbrella can scale and recycle legacy non OpenFlow core switch to reduce migration cost. Into the testing tools lacuna we launch the Open Source Network Tester (OSNT), a fully open-source traffic generator and capture system. Additionally, our approach has demonstrated lower-cost than comparable commercial systems while achieving comparable levels of precision and accuracy; all within an open-source framework extensible with new features to support new applications, while permitting validation and review of the implementation. And we presents the integration of OpenFLow Operations Per Second (OFLOPS), an OpenFlow switch evaluation platform, with the OSNT platform, a hardware-accelerated traffic generation and capturing platform. What is better justification than a real deployment ? We demonstrated the real flexibility and benefit of the Umbrella architecture persuading ten Internet Operators to migrate the entire Toulouse IXP. The hardware testing tools we have developed have been used to qualify the hardware who have been deployed in production. The TouIX is running stable from a year. It is fully managed and monitored through a single web application removing all the legacy complex management systems

    FRAME: frame routing and manipulation engine

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    This research reports on the design and implementation of FRAME: an embedded hardware network processing platform designed to perform network frame manipulation and monitoring. This is possible at line speeds compliant with the IEEE 802.3 Ethernet standard. The system provides frame manipulation functionality to aid in the development and implementation of network testing environments. Platform cost and ease of use are both considered during design resulting in fabrication of hardware and the development of Link, a Domain Specific Language used to create custom applications that are compatible with the platform. Functionality of the resulting platform is shown through conformance testing of designed modules and application examples. Throughput testing showed that the peak throughput achievable by the platform is limited to 86.4 Mbit/s, comparable to commodity 100 Mbit hardware and the total cost of the prototype platform ranged between 220and220 and 254

    On the Exploration of FPGAs and High-Level Synthesis Capabilities on Multi-Gigabit-per-Second Networks

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    Tesis doctoral inédita leída en la Universidad Autónoma de Madrid, Escuela Politécnica Superior, Departamento de Tecnología Electrónica y de las Comunicaciones. Fecha de lectura: 24-01-2020Traffic on computer networks has faced an exponential grown in recent years. Both links and communication equipment had to adapt in order to provide a minimum quality of service required for current needs. However, in recent years, a few factors have prevented commercial off-the-shelf hardware from being able to keep pace with this growth rate, consequently, some software tools are struggling to fulfill their tasks, especially at speeds higher than 10 Gbit/s. For this reason, Field Programmable Gate Arrays (FPGAs) have arisen as an alternative to address the most demanding tasks without the need to design an application specific integrated circuit, this is in part to their flexibility and programmability in the field. Needless to say, developing for FPGAs is well-known to be complex. Therefore, in this thesis we tackle the use of FPGAs and High-Level Synthesis (HLS) languages in the context of computer networks. We focus on the use of FPGA both in computer network monitoring application and reliable data transmission at very high-speed. On the other hand, we intend to shed light on the use of high level synthesis languages and boost FPGA applicability in the context of computer networks so as to reduce development time and design complexity. In the first part of the thesis, devoted to computer network monitoring. We take advantage of the FPGA determinism in order to implement active monitoring probes, which consist on sending a train of packets which is later used to obtain network parameters. In this case, the determinism is key to reduce the uncertainty of the measurements. The results of our experiments show that the FPGA implementations are much more accurate and more precise than the software counterpart. At the same time, the FPGA implementation is scalable in terms of network speed — 1, 10 and 100 Gbit/s. In the context of passive monitoring, we leverage the FPGA architecture to implement algorithms able to thin cyphered traffic as well as removing duplicate packets. These two algorithms straightforward in principle, but very useful to help traditional network analysis tools to cope with their task at higher network speeds. On one hand, processing cyphered traffic bring little benefits, on the other hand, processing duplicate traffic impacts negatively in the performance of the software tools. In the second part of the thesis, devoted to the TCP/IP stack. We explore the current limitations of reliable data transmission using standard software at very high-speed. Nowadays, the network is becoming an important bottleneck to fulfill current needs, in particular in data centers. What is more, in recent years the deployment of 100 Gbit/s network links has started. Consequently, there has been an increase scrutiny of how networking functionality is deployed, furthermore, a wide range of approaches are currently being explored to increase the efficiency of networks and tailor its functionality to the actual needs of the application at hand. FPGAs arise as the perfect alternative to deal with this problem. For this reason, in this thesis we develop Limago an FPGA-based open-source implementation of a TCP/IP stack operating at 100 Gbit/s for Xilinx’s FPGAs. Limago not only provides an unprecedented throughput, but also, provides a tiny latency when compared to the software implementations, at least fifteen times. Limago is a key contribution in some of the hottest topic at the moment, for instance, network-attached FPGA and in-network data processing

    Fast Packet Processing on High Performance Architectures

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    The rapid growth of Internet and the fast emergence of new network applications have brought great challenges and complex issues in deploying high-speed and QoS guaranteed IP network. For this reason packet classication and network intrusion detection have assumed a key role in modern communication networks in order to provide Qos and security. In this thesis we describe a number of the most advanced solutions to these tasks. We introduce NetFPGA and Network Processors as reference platforms both for the design and the implementation of the solutions and algorithms described in this thesis. The rise in links capacity reduces the time available to network devices for packet processing. For this reason, we show different solutions which, either by heuristic and randomization or by smart construction of state machine, allow IP lookup, packet classification and deep packet inspection to be fast in real devices based on high speed platforms such as NetFPGA or Network Processors

    Time Synchronization Solution for FPGA-based Distributed Network Monitoring

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    Distributed network monitoring solutions face various challenges with the increase of line speed, the extending variety of protocols, and new services with complex KPIs. This paper addresses one part of the first challenge: faster line speed necessitates time-stamping with higher granularity and higher precision than ever. Proper, system-wide time-stamping is inevitable for network monitoring and traffic analysis point of view. It is hard to find feasible time synchronization solutions for those systems that have nation-wide, physically distributed probes. Current networking equipment reside in server rooms, and have many legacy nodes. Access to GPS signal is complicated in these places, and Precision Time Protocol (PTP) does not seem to be supported by all network nodes in the near future – so high precision time-stamping is indeed a current problem. This paper suggests a novel, practical solution to overcome the obstacles. The core idea is that in real-life, distributed network monitoring systems operate with a few, finite number of probeclusters, and their site should have a precise clock provided by PTP or GPS somewhere in the building. The distribution of time information within a site is still troublesome, even within a server rack. This paper presents a closed control loop solution implemented in an FPGA-based device in order to minimize the jitter, and compensate the calculated delay

    Sniffer gigabit ethernet em hardware para sistemas de tempo-real

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    Mestrado em Engenharia Electrónica e TelecomunicaçõesAs ferramentas habituais de análise do comportamento lógico e temporal de uma rede de comunicações, conhecidas popularmente por Sniffers, são satisfatórias para as redes de uso geral. No entanto, não correspondem aos requisitos concretos de alguns protocolos de tempo-real, nomeadamente no que concerne à resolução e precisão das medições dos instantes de transmissão e recepção de mensagens. Esta incapacidade tem a sua origem no facto de estas ferramentas serem aplicações em software, a correr em computadores comuns. Nestes, as suas características multitarefa e o próprio mecanismo de “time-stamping” das mensagens não são apropriados para requisitos de tempo-real. Como resposta a esta limitação, desenvolveu-se um Sniffer Ethernet em Hardware, recorrendo-se a FPGAs e a núcleos sintetizáveis de propriedade intelectual. A ferramenta desenvolvida é capaz de capturar tráfego Gigabit num segmento Ethernet realizando o time-stamping das mensagens em hardware. Os dados são depois transferidos para um computador novamente pela via Ethernet. Do lado do PC os dados são primeiro reconhecidos pelo popular software analisador de dados, Wireshark. Seguidamente, com recurso a ferramentas de software desenvolvidas, os dados são exportados e convertidos para um formato mais conveniente para serem analisados em ferramentas de cálculo. A ferramenta mostrou ser capaz de capturar todo o tráfego procedente de uma porta Ethernet com uma precisão temporal de 8ns e um jitter de 16ns.The standard tools for analysis of the logical and temporal behavior of a communication network, commonly known as Sniffers, are satisfactory for general purpose networks. However, they are insufficient for the specific requisites of some real-time protocols, namely in what concerns the resolution and temporal precision associated with the time-stamping of the arriving messages. This incapacity has its source in the fact that these tools are software based, running in common computers. The way time-stamping ins performed on these machines, as well as the multitask features associated with them are not appropriate for the requisites of real-time systems. As an answer to this limitation, a Gigabit Ethernet hardware based was developed on an FPGA and making use of intellectual Property Cores. The tool developed is capable if capturing Gigabit Ethernet traffic on an Ethernet Link, measuring the time-stamping on hardware. The data is then transferred again through an Ethernet Port. On the PC side, all data is first captured by the popular software data analyzer, Wireshark. Next, making use of software tools developed, the data is exported to a convenient format, in order to be analyzed by math tools. The tool proved to be capable of capturing all the traffic coming from an Ethernet port with an 8ns resolution and 16ns jitter
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