Static random-access memory designs based on different FinFET at lower technology node (7nm)

Title from PDF of title page viewed January 15, 2020Thesis advisor: Masud H ChowdhuryVitaIncludes bibliographical references (page 50-57)Thesis (M.S.)--School of Computing and Engineering. University of Missouri--Kansas City, 2019The Static Random-Access Memory (SRAM) has a significant performance impact on current nanoelectronics systems. To improve SRAM efficiency, it is important to utilize emerging technologies to overcome short-channel effects (SCE) of conventional CMOS. FinFET devices are promising emerging devices that can be utilized to improve the performance of SRAM designs at lower technology nodes. In this thesis, I present detail analysis of SRAM cells using different types of FinFET devices at 7nm technology. From the analysis, it can be concluded that the performance of both 6T and 8T SRAM designs are improved. 6T SRAM achieves a 44.97% improvement in the read energy compared to 8T SRAM. However, 6T SRAM write energy degraded by 3.16% compared to 8T SRAM. Read stability and write ability of SRAM cells are determined using Static Noise Margin and N- curve methods. Moreover, Monte Carlo simulations are performed on the SRAM cells to evaluate process variations. Simulations were done in HSPICE using 7nm Asymmetrical Underlap FinFET technology. The quasiplanar FinFET structure gained considerable attention because of the ease of the fabrication process [1] – [4]. Scaling of technology have degraded the performance of CMOS designs because of the short channel effects (SCEs) [5], [6]. Therefore, there has been upsurge in demand for FinFET devices for emerging market segments including artificial intelligence and cloud computing (AI) [8], [9], Internet of Things (IoT) [10] – [13] and biomedical [17] –[18] which have their own exclusive style of design. In recent years, many Underlapped FinFET devices were proposed to have better control of the SCEs in the sub-nanometer technologies [3], [4], [19] – [33]. Underlap on either side of the gate increases effective channel length as seen by the charge carriers. Consequently, the source-to-drain tunneling probability is improved. Moreover, edge direct tunneling leakage components can be reduced by controlling the electric field at the gate-drain junction . There is a limitation on the extent of underlap on drain or source sides because the ION is lower for larger underlap. Additionally, FinFET based designs have major width quantization issue. The width of a FinFET device increases only in quanta of silicon fin height (HFIN) [4]. The width quantization issue becomes critical for ratioed designs like SRAMs, where proper sizing of the transistors is essential for fault-free operation. FinFETs based on Design/Technology Co-Optimization (DTCO_F) approach can overcome these issues [38]. DTCO_F follows special design rules, which provides the specifications for the standard SRAM cells with special spacing rules and low leakages. The performances of 6T SRAM designs implemented by different FinFET devices are compared for different pull-up, pull down and pass gate transistor (PU: PD:PG) ratios to identify the best FinFET device for high speed and low power SRAM applications. Underlapped FinFETs (UF) and Design/Technology Co-Optimized FinFETs (DTCO_F) are used for the design and analysis. It is observed that with the PU: PD:PG ratios of 1:1:1 and 1:5:2 for the UF-SRAMs the read energy has degraded by 3.31% and 48.72% compared to the DTCO_F-SRAMs, respectively. However, the read energy with 2:5:2 ratio has improved by 32.71% in the UF-SRAM compared to the DTCO_F-SRAMs. The write energy with 1:1:1 configuration has improved by 642.27% in the UF-SRAM compared to the DTCO_F-SRAM. On the other hand, the write energy with 1:5:2 and 2:5:2 configurations have degraded by 86.26% and 96% in the UF-SRAMs compared to the DTCO_F-SRAMs. The stability and reliability of different SRAMs are also evaluated for 500mV supply. From the analysis, it can be concluded that Asymmetrical Underlapped FinFET is better for high-speed applications and DTCO FinFET for low power applications.Introduction -- Next generation high performance device: FinFET -- FinFET based SRAM bitcell designs -- Benchmarking of UF-SRAMs and DTCO-F-SRAMS -- Collaborative project -- Internship experience at INTEL and Marvell Semiconductor -- Conclusion and future wor

Sub-10nm Transistors for Low Power Computing: Tunnel FETs and Negative Capacitance FETs

One of the major roadblocks in the continued scaling of standard CMOS technology is its alarmingly high leakage power consumption. Although circuit and system level methods can be employed to reduce power, the fundamental limit in the overall energy efficiency of a system is still rooted in the MOSFET operating principle: an injection of thermally distributed carriers, which does not allow subthreshold swing (SS) lower than 60mV/dec at room temperature. Recently, a new class of steep-slope devices like Tunnel FETs (TFETs) and Negative-Capacitance FETs (NCFETs) have garnered intense interest due to their ability to surpass the 60mV/dec limit on SS at room temperature. The focus of this research is on the simulation and design of TFETs and NCFETs for ultra-low power logic and memory applications. Using full band quantum mechanical model within the Non-Equilibrium Greens Function (NEGF) formalism, source-underlapping has been proposed as an effective technique to lower the SS in GaSb-InAs TFETs. Band-tail states, associated with heavy source doping, are shown to significantly degrade the SS in TFETs from their ideal value. To solve this problem, undoped source GaSb-InAs TFET in an i-i-n configuration is proposed. A detailed circuit-to-system level evaluation is performed to investigate the circuit level metrics of the proposed devices. To demonstrate their potential in a memory application, a 4T gain cell (GC) is proposed, which utilizes the low-leakage and enhanced drain capacitance of TFETs to realize a robust and long retention time GC embedded-DRAMs. The device/circuit/system level evaluation of proposed TFETs demonstrates their potential for low power digital applications. The second part of the thesis focuses on the design space exploration of hysteresis-free Negative Capacitance FETs (NCFETs). A cross-architecture analysis using HfZrOx ferroelectric (FE-HZO) integrated on bulk MOSFET, fully-depleted SOI-FETs, and sub-10nm FinFETs shows that FDSOI and FinFET configurations greatly benefit the NCFET performance due to their undoped body and improved gate-control which enables better capacitance matching with the ferroelectric. A low voltage NC-FinFET operating down to 0.25V is predicted using ultra-thin 3nm FE-HZO. Next, we propose one-transistor ferroelectric NOR type (Fe-NOR) non-volatile memory based on HfZrOx ferroelectric FETs (FeFETs). The enhanced drain-channel coupling in ultrashort channel FeFETs is utilized to dynamically modulate memory window of storage cells thereby resulting in simple erase-, program-and read-operations. The simulation analysis predicts sub-1V program/erase voltages in the proposed Fe-NOR memory array and therefore presents a significantly lower power alternative to conventional FeRAM and NOR flash memories

Novel High Performance Ultra Low Power Static Random Access Memories (SRAMs) Based on Next Generation Technologies

Title from PDF of title page viewed January 27, 2021Dissertation advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (page 107-120)Thesis (Ph.D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2019Next Big Thing Is Surely Small: Nanotechnology Can Bring Revolution. Nanotechnology leads the world towards many new applications in various fields of computing, communication, defense, entertainment, medical, renewable energy and environment. These nanotechnology applications require an energy-efficient memory system to compute and process. Among all the memories, Static Random Access Memories (SRAMs) are high performance memories and occupies more than 50% of any design area. Therefore, it is critical to design high performance and energy-efficient SRAM design. Ultra low power and high speed applications require a new generation memory capable of operating at low power as well as low execution time. In this thesis, a novel 8T SRAM design is proposed that offers significantly faster access time and lowers energy consumption along with better read stability and write ability. The proposed design can be used in the conventional SRAM as well as in computationally intensive applications like neural networks and machine learning classifiers [1]-[4]. Novel 8T SRAM design offers higher energy efficiency, reliability, robustness and performance compared to the standard 6T and other existing 8T and 9T designs. It offers the advantages of a 10T SRAM without the additional area, delay and power overheads of the 10T SRAM. The proposed 8T SRAM would be able to overcome many other limitations of the conventional 6T and other 7T, 8T and 9T designs. The design employs single bitline for the write operation, therefore the number of write drivers are reduced. The defining feature of the proposed 8T SRAM is its hybrid design, which is the combination of two techniques: (i) the utilization of single-ended bitline and (ii) the utilization of virtual ground. The single-ended bitline technique ensures separate read and write operations, which eventually reduces the delay and power consumption during the read and write operations. It's independent read and write paths allow the use of the minimum sized access transistors and aid in a disturb-free read operation. The virtual ground weakens the positive feedback in the SRAM cell and improves its write ability. The virtual ground technique is also used to reduce leakages. The proposed design does not require precharging the bitlines for the read operation, which reduces the area and power overheads of the memory system by eliminating the precharging circuit. The design isolates the storage node from the read path, which improves the read stability. For reliability study, we have investigated the static noise margin (SNM) of the proposed 8T SRAM, for which, we have used two methods – (i) the traditional SNM method with the butterfly curve, (ii) the N-curve method A comparative analysis is performed between the proposed and the existing SRAM designs in terms of area, total power consumption during the read and write operations, and stability and reliability. All these advantages make the proposed 8T SRAM design an ideal candidate for the conventional and computationally intensive applications like machine learning classifier and deep learning neural network. In addition to this, there is need for next generation technologies to design SRAM memory because the conventional CMOS technology is approaching its physical and performance boundaries and as a consequence, becoming incompatible with ultra-low-power applications. Emerging devices such as Tunnel Field Effect Transistor (TFET)) and Graphene Nanoribbon Field Effect Transistor (GNRFET) devices are highly potential candidates to overcome the limitations of MOSFET because of their ability to achieve subthreshold slopes below 60 mV/decade and very low leakage currents [6]-[9]. This research also explores novel TFET and GNRFET based 6T SRAM. The thesis evaluates the standby leakage power in the Tunnel FET (TFET) based 6T SRAM cell for different pull-up, pull-down, and pass-gate transistors ratios (PU: PD: PG) and compared to 10nm FinFET based 6T SRAM designs. It is observed that the 10nm TFET based SRAMs have 107.57%, 163.64%, and 140.44% less standby leakage power compared to the 10nm FinFET based SRAMs when the PU: PD: PG ratios are 1:1:1, 1:5:2 and 2:5:2, respectively. The thesis also presents an analysis of the stability and reliability of sub-10nm TFET based 6T SRAM circuit with a reduced supply voltage of 500mV. The static noise margin (SNM), which is a critical measure of SRAM stability and reliability, is determined for hold, read and write operations of the 6T TFET SRAM cell. The robustness of the optimized TFET based 6T SRAM circuit is also evaluated at different supply voltages. Simulations were done in HSPICE and Cadence tools. From the analysis, it is clear that the main advantage of the TFET based SRAM would be the significant improvement in terms of leakage or standby power consumption. Compared to the FinFET based SRAM the standby leakage power of the T-SRAMs are 107.57%, 163.64%, and 140.44% less for 1:1:1, 1:5:2 and 2:5:2 configurations, respectively. Since leakage/standby power is the primary source of power consumption in the SRAM, and the overall system energy efficiency depends on SRAM power consumption, TFET based SRAM would lead to massive improvement of the energy efficiency of the system. Therefore, T-SRAMs are more suitable for ultra-low power applications. In addition to this, the thesis evaluates the standby leakage power of types of Graphene Nanoribbon FETs based 6T SRAM bitcell and compared to 10nm FinFET based 6T SRAM bitcell. It is observed that the 10nm MOS type GNRFET based SRAMs have 16.43 times less standby leakage power compared to the 10nm FinFET based SRAMs. The double gate SB-GNRFET based SRAM consumes 1.35E+03 times less energy compared to the 10nm FinFET based SRAM during write. However, during read double gate SB-GNRFET based SRAM consume 15 times more energy than FinFET based SRAM. It is also observed that GNRFET based SRAMs are more stable and reliable than FinFET based SRAM.Introduction -- Background -- Novel High Performance Ultra Low Power SRAM Design -- Tunnel FET Based SRAM Design -- Graphene Nanoribbon FET Based SRAM Design -- Double-gate FDSOI Based SRAM Designs -- Novel CNTFET and MEMRISTOR Based Digital Designs -- Conclusio

On-chip Voltage Regulator– Circuit Design and Automation

Title from PDF of title page viewed May 24, 2021Dissertation advisors: Masud H Chowdhury and Yugyung LeeVitaIncludes bibliographical references (page 106-121)Thesis (Ph.D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2021With the increase of density and complexity of high-performance integrated circuits and systems, including many-core chips and system-on-chip (SoC), it is becoming difficult to meet the power delivery and regulation requirements with off-chip regulators. The off-chip regulators become a less attractive choice because of the higher overheads and complexity imposed by the additional wires, pins, and pads. The increased I2R loss makes it challenging to maintain the integrity of different voltage domains under a lower supply voltage environment in the smaller technology nodes. Fully integrated on-chip voltage regulators have proven to be an effective solution to mitigate power delivery and integrity issues. Two types of regulators are considered as most promising for on-chip implementation: (i) the low-drop-out (LDO) regulator and (ii) the switched-capacitor (SC)regulator. The first part of our research mainly focused on the LDO regulator. Inspired by the recent surge of interest for cap-less voltage regulators, we presented two fully on-chip external capacitor-less low-dropout voltage regulator design. The second part of this proposal explores the complexity of designing each block of the regulator/analog circuit and proposed a design methodology for analog circuit synthesis using simulation and learning-based approach. As the complexity is increasing day-by-day in an analog circuit, hierarchical flow mostly uses for design automation. In this work, we focused mainly on Circuit-level, one of the significant steps in the flow. We presented a novel, efficient circuit synthesis flow based on simulation and learning-based optimization methods. The proposed methodology has two phases: the learning phase and the evaluation phase. Random forest, a supervised learning is used to reduce the sample points in the design space and iteration number during the learning phase. Additionally, symmetric constraints are used further to reduce the iteration number during the sizing process. We introduced a three-step circuit synthesis flow to automate the analog circuit design. We used H-spice as a simulation tool during the evaluation phase of the proposed methodology. The three most common analog circuits are chosen: single-stage differential amplifier, operational transconductance amplifier, and two-stage differential amplifier to verify the algorithm. The tool is developed in Python, and the technology we used is0.6um. We also verified the optimized result in Cadence Virtuoso.Introduction -- On-chip power delivery system -- Fundamentals of on-chip voltage regulator -- LDO design in 45NM technology -- LDO design in technology -- Analog design automation -- Proposed analog design methodology -- Energy efficient FDSOI and FINFET based power gating circuit using data retention transistor -- Conclusion and future wor

Vertical III-V Nanowire Transistors for Low-Power Electronics

Power dissipation has been the major challenge in the downscaling of transistor technology. Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) have struggled to keep a low power consumption while still maintaining a high performance due to the low carrier mobilities of Si but also due to their inherent minimum inverse subthreshold slope (S ≥ 60 mV/dec) which is limited by thermionic emission. This thesis work studied the capabilities and limitations of III-V based vertical nanowire n-type Tunneling Field-Effect Transistor (TFET) and p-type MOSFET (PMOS). InAs/InGaAsSb/GaSb heterojunction was employed in the whole study. The main focus was to understand the influence of the device fabrication processes and the structural factors of the nanowires such as band alignment, composition and doping on the electrical performance of the TFET. Optimizations of the device processes including spacer technology improvement, Equivalent Oxide Thickness (EOT) downscaling, and gate underlap/overlap were explored utilizing structural characterizations. Systematic fine tuning of the band alignment of the tunnel junction resultedin achieving the best performing sub-40 mV/dec TFETs with S = 32 mV/decand ION = 4μA/μm for IOFF = 1 nA/μm at VDS = 0.3 V. The suitability of employing TFET for electronic applications at cryogenic temperatures has been explored utilizing experimental device data. The impact of the choice of heterostructure and dopant incorporation were investigated to identify the optimum operating temperature and voltage in different temperature regimes. A novel gate last process self-aligning the gate and drain contacts to the intrinsic and doped segments, respectively was developed for vertical InGaAsSb-GaAsSb core-shell nanowire transistors leading to the first sub-100 mV/dec PMOS with S = 75 mV/dec, significant ION/ IOFF = 104 and IMIN < 1 nA/μm at VDS = -0.5 V

Strain integration and performance optimization in sub-20nm FDSOI CMOS technology

La technologie CMOS à base de Silicium complètement déserté sur isolant (FDSOI) est considérée comme une option privilégiée pour les applications à faible consommation telles que les applications mobiles ou les objets connectés. Elle doit cela à son architecture garantissant un excellent comportement électrostatique des transistors ainsi qu'à l'intégration de canaux contraints améliorant la mobilité des porteurs. Ce travail de thèse explore des solutions innovantes en FDSOI pour nœuds 20nm et en deçà, comprenant l'ingénierie de la contrainte mécanique à travers des études sur les matériaux, les dispositifs, les procédés d'intégration et les dessins des circuits. Des simulations mécaniques, caractérisations physiques (µRaman), et intégrations expérimentales de canaux contraints (sSOI, SiGe) ou de procédés générant de la contrainte (nitrure, fluage de l'oxyde enterré) nous permettent d'apporter des recommandations pour la technologie et le dessin physique des transistors en FDSOI. Dans ce travail de thèse, nous avons étudié le transport dans les dispositifs à canal court, ce qui nous a amené à proposer une méthode originale pour extraire simultanément la mobilité des porteurs et la résistance d'accès. Nous mettons ainsi en évidence la sensibilité de la résistance d'accès à la contrainte que ce soit pour des transistors FDSOI ou nanofils. Nous mettons en évidence et modélisons la relaxation de la contrainte dans le SiGe apparaissant lors de la gravure des motifs et causant des effets géométriques (LLE) dans les technologies FDSOI avancées. Nous proposons des solutions de type dessin ainsi que des solutions technologiques afin d'améliorer la performance des cellules standard digitales et de mémoire vive statique (SRAM). En particulier, nous démontrons l'efficacité d'une isolation duale pour la gestion de la contrainte et l'extension de la capacité de polarisation arrière, qui un atout majeur de la technologie FDSOI. Enfin, la technologie 3D séquentielle rend possible la polarisation arrière en régime dynamique, à travers une co-optimisation dessin/technologie (DTCO).The Ultra-Thin Body and Buried oxide Fully Depleted Silicon On Insulator (UTBB FDSOI) CMOS technology has been demonstrated to be highly efficient for low power and low leakage applications such as mobile, internet of things or wearable. This is mainly due to the excellent electrostatics in the transistor and the successful integration of strained channel as a carrier mobility booster. This work explores scaling solutions of FDSOI for sub-20nm nodes, including innovative strain engineering, relying on material, device, process integration and circuit design layout studies. Thanks to mechanical simulations, physical characterizations and experimental integration of strained channels (sSOI, SiGe) and local stressors (nitride, oxide creeping, SiGe source/drain) into FDSOI CMOS transistors, we provide guidelines for technology and physical circuit design. In this PhD, we have in-depth studied the carrier transport in short devices, leading us to propose an original method to extract simultaneously the carrier mobility and the access resistance and to clearly evidence and extract the strain sensitivity of the access resistance, not only in FDSOI but also in strained nanowire transistors. Most of all, we evidence and model the patterning-induced SiGe strain relaxation, which is responsible for electrical Local Layout Effects (LLE) in advanced FDSOI transistors. Taking into account these geometrical effects observed at the nano-scale, we propose design and technology solutions to enhance Static Random Access Memory (SRAM) and digital standard cells performance and especially an original dual active isolation integration. Such a solution is not only stress-friendly but can also extend the powerful back-bias capability, which is a key differentiating feature of FDSOI. Eventually the 3D monolithic integration can also leverage planar Fully-Depleted devices by enabling dynamic back-bias owing to a Design/Technology Co-Optimization

Implémentation de PCM (Process Compact Models) pour l’étude et l’amélioration de la variabilité des technologies CMOS FDSOI avancées

Recently, the race for miniaturization has seen its growth slow because of technological challenges it entails. These barriers include the increasing impact of the local variability and processes from the increasing complexity of the manufacturing process and miniaturization, in addition to the difficult of reducing the channel length. To address these challenges, new architectures, very different from the traditional one (bulk), have been proposed. However these new architectures require more effort to be industrialized. Increasing complexity and development time require larger financial investments. In fact there is a real need to improve the development and optimization of devices. This work gives some tips in order to achieve these goals. The idea to address the problem is to reduce the number of trials required to find the optimal manufacturing process. The optimal process is one that results in a device whose performance and dispersion reach the predefined aims. The idea developed in this thesis is to combine TCAD tool and compact models in order to build and calibrate what is called PCM (Process Compact Model). PCM is an analytical model that establishes linkages between process and electrical parameters of the MOSFET. It takes both the benefits of TCAD (since it connects directly to the process parameters electrical parameters) and compact (since the model is analytic and therefore faster to calculate). A sufficiently robust predictive and PCM can be used to optimize performance and overall variability of the transistor through an appropriate optimization algorithm. This approach is different from traditional development methods that rely heavily on scientific expertise and successive tests in order to improve the system. Indeed this approach provides a deterministic and robust mathematical framework to the problem. The concept was developed, tested and applied to transistors 28 and 14 nm FD-SOI and to TCAD simulations. The results are presented and recommendations to implement it at industrial scale are provided. Some perspectives and applications are likewise suggested.Récemment, la course à la miniaturisation a vue sa progression ralentir à cause des défis technologiques qu’elle implique. Parmi ces obstacles, on trouve l’impact croissant de la variabilité local et process émanant de la complexité croissante du processus de fabrication et de la miniaturisation, en plus de la difficulté à réduire la longueur du canal. Afin de relever ces défis, de nouvelles architectures, très différentes de celle traditionnelle (bulk), ont été proposées. Cependant ces nouvelles architectures demandent plus d’efforts pour être industrialisées. L’augmentation de la complexité et du temps de développement requièrent de plus gros investissements financier. De fait il existe un besoin réel d’améliorer le développement et l’optimisation des dispositifs. Ce travail donne quelques pistes dans le but d’atteindre ces objectifs. L’idée, pour répondre au problème, est de réduire le nombre d’essai nécessaire pour trouver le processus de fabrication optimal. Le processus optimal est celui qui conduit à un dispositif dont les performances et leur dispersion atteignent les objectifs prédéfinis. L’idée développée dans cette thèse est de combiner l’outil TCAD et les modèles compacts dans le but de construire et calibrer ce que l’on appelle un PCM (Process Compact Model). Un PCM est un modèle analytique qui établit les liens entre les paramètres process et électriques du MOSFET. Il tire à la fois les bénéfices de la TCAD (puisqu’il relie directement les paramètres process aux paramètres électriques) et du modèle compact (puisque le modèle est analytique et donc rapide à calculer). Un PCM suffisamment prédictif et robuste peut être utilisé pour optimiser les performances et la variabilité globale du transistor grâce à un algorithme d’optimisation approprié. Cette approche est différente des méthodes de développement classiques qui font largement appel à l’expertise scientifique et à des essais successifs dans le but d’améliorer le dispositif. En effet cette approche apporte un cadre mathématique déterministe et robuste au problème.Le concept a été développé, testé et appliqué aux transistors 28 et 14 nm FD-SOI ainsi qu’aux simulations TCAD. Les résultats sont exposés ainsi que les recommandations nécessaires pour implémenter la technique à échelle industrielle. Certaines perspectives et applications sont de même suggérées

Compact Models for Integrated Circuit Design

This modern treatise on compact models for circuit computer-aided design (CAD) presents industry standard models for bipolar-junction transistors (BJTs), metal-oxide-semiconductor (MOS) field-effect-transistors (FETs), FinFETs, and tunnel field-effect transistors (TFETs), along with statistical MOS models. Featuring exercise problems at the end of each chapter and extensive references at the end of the book, the text supplies fundamental and practical knowledge necessary for efficient integrated circuit (IC) design using nanoscale devices. It ensures even those unfamiliar with semiconductor physics gain a solid grasp of compact modeling concepts

Novel III-V compound semiconductor technologies for low power digital logic applications

As silicon (Si) complementary metal oxide semiconductor (CMOS) technology continues to scale into the 10 nm node, chip power consumption is approaching 200 W/cm2 and any further increase is unsustainable. Incorporating III-V compound semiconductor n-type devices into future CMOS generations could allow for the the reduction in supply voltage, and therefore, power consumption, while simultaneously improving on-state performance. The advanced state of Si CMOS places stringent demands on III-V devices, however: the current 14 nm Si tri-gate devices employ high aspect ratio, densely spaced fins which serve to significantly increase current per chip surface area. III-V devices need to significantly out perform state of the art Si devices in order to merit their disruptive incorporation into the well established CMOS process. This necessitates that they too exploit the vertical dimension. To this end, this thesis reports on the fabrication, measurement and analysis of high aspect ratio junctionless InGaAs FinFETs. The junctionless architecture was first demonstrated in 2010 and was shown to circumvent pro- hibitive fabrication challenges for devices with ultra short gate lengths. This work investigated the impact of fin width on both the on and off-state performance of 200 nm gate length devices, with nominal fin widths of 10, 15 and 20 nm. Excellent subthreshold performance was demonstrated, with the narrowest fin width exhibiting a minimum subthreshold swing (SS) of 73 mV/Dec., and an average SS of 80 mV/Dec. over two decades of current. A maximum on-current, Ion, of 80.51 μA/cm2 was measured at a gate overdrive of 0.5 V from an off-state current, Ioff, of 100 nA/cm2 and a drain voltage, Vd, of 0.5 V, with current normalised by gated perimeter. This is competitive with other III-V junctionless devices at similar gate lengths. With current normalised to base fin width, however, Ion increases to 371.8 μA/cm2, which is a record value among equivalently normalised non-planar III-V junctionless devices at any gate length. This technology, therefore, clearly demonstrates the feasibility of incorporating scaled, etched InGaAs fins into future logic generations. Perhaps the greatest bottleneck to the incorporation of III-V compounds into future CMOS technology nodes, however, is the lack of a suitable III-V PMOS candidate: co-integrating different material systems onto a common substate incurs great fabrication complexity, and therefore, cost. III-V antimonides, however, have recently emerged as promising candidates for III-V PMOS and exhibit the highest bulk electron mobility of all III-Vs in addition to a hole mobility second only to germanium. InGaSb ternary compounds have been shown to offer the best combined performance for electrons and holes in the same material, and as such, have the potential to the enable the most simplistic incarnation of III-V CMOS; provided, of course, that is possible to form a gate stack to both device polarities with sufficient electrical properties. To date, however, there has been no investigation into the high-k dielectric interface to InGaSb. To this end, this thesis presents results of the first investigation into the impact of in-situ H2 plasma exposure on the electrical properties of the p/n-In0.3Ga0.7Sb-Al2O3 interface. The parameter space was explored systematically in terms of H2 plasma power and exposure time, and further, the impact of impact of in-situ trimethylaluminium (TMA) pre-cleaning and annealing in forming gas was assessed. Metal oxide semiconductor capacitors (MOSCAPs) were fabricated subsequent to H2 plasma processing and Al2O3 deposition, and the correspond- ing capacitance-voltage and conductance-voltage measurements were analysed both qualita- tively and quantitatively via the simulation of an equivalent circuit model. X-Ray photoelectron spectroscopy (XPS) analysis of samples processed as part of the plasma power series revealed a combination of ex-situ HCl cleaning and in-situ H2 plasma exposure to completely remove In and Sb sub oxides, with the Ga-O content reduced to Ga-O:InGaSb <0.1. The optimal process, which included ex-situ HCl surface cleaning, in-situ H2 plasma and TMA pre-cleaning, and a post gate metal forming gas anneal, was unequivocally demonstrated to yield a fully unpinnned MOS interface with both n and p-type MOSCAPs explicitly demonstrating a genuine minority carrier response. Interface state and border trap densities were extracted, with a minimum Dit of 1.73x1012 cm-2 eV-1 located at ~110 meV below the conduction band edge and peak border trap densities approximately aligned with the valence and conduction band edges of 3x1019 cm-3 eV-1 and 6.5x1019 cm-3 eV-1 respectively. These results indicate that the optimal gate stack process is indeed applicable to both p and n- type InGaSb MOSFETs, and therefore, represent a critical advancement towards achieving high performance III-V CMOS

Optimisation des jonctions de dispositifs (FDSOI, TriGate) fabriqués à faible température pour l’intégration 3D séquentielle

3D sequential integration is a promising candidate for the scaling sustainability for technological nodes beyond 14 nm. The main challenge is the development of a low temperature process for the top transistor level that enables to avoid the degradation of the bottom transistor level. The most critical process step for the top transistor level fabrication is the dopant activation that is usually performed at temperature higher than 1000 °C. In the frame of this Ph.D. work, different solutions for the dopant activation optimization at low temperature (below 600 °C) are proposed and integrated in FDSOI and TriGate devices. The technique chosen for the dopant activation at low temperature is the solid phase epitaxial regrowth. First, doping conditions have been optimized in terms of activation level and process time for low temperatures (down to 450 °C) anneals. The obtained conditions have been implemented in FDSOI and TriGate devices leading to degraded electrical results compared to the high temperature process of reference (above 1000 °C). By means of TCAD simulation and electrical measurements comparison, the critical region of the transistor in terms of activation appears to be below the offset spacer. The extension first integration scheme is then shown to be the best candidate to obtain high performance low temperature devices. Indeed, by performing the doping implantation before the raised source and drain epitaxial growth, the absence of diffusion at low temperature can be compensated. This conclusion can be extrapolated for TriGate and FinFET on insulator devices. Extension first integration scheme has been demonstrated for the first time on N and PFETs in 14 nm FDSOI technology showing promising results in terms of performance. This demonstration evidences that the two challenges of this integration i.e. the partial amorphization of very thin films and the epitaxy regrowth on implanted access are feasible. Finally, heated implantation has been investigated as a solution to dope thin access regions without full amorphization, which is particularly critical for FDSOI and FinFET devices. The as-implanted activation levels are shown to be too low to obtain high performance devices and the heated implantation appears a promising candidate for low temperature devices if used in combination with an alternative activation mechanism.L’intégration 3D séquentielle représente une alternative potentielle à la réduction des dimensions afin de gagner encore en densité d’une génération à la suivante. Le principal défi concerne la fabrication du transistor de l’étage supérieur avec un faible budget thermique; ceci afin d’éviter la dégradation du niveau inférieur. L’étape de fabrication la plus critique pour la réalisation du niveau supérieur est l’activation des dopants. Celle-ci est généralement effectuée par recuit à une température supérieure à 1000 °C. Dans ce contexte, cette thèse propose des solutions pour activer les dopants à des températures inférieures à 600 °C par la technique dite de recristallisation en phase solide. Les conditions de dopage ont été optimisées pour améliorer le niveau d’activation et le temps de recuit tout en réduisant la température d’activation jusqu’à 450°C. Les avancées obtenues ont été implémentées sur des dispositifs avancés FDSOI et TriGate générant des dispositifs avec des performances inférieures aux références fabriquées à hautes températures (supérieures à 1000 °C). En utilisant des simulations TCAD et en les comparant aux mesures électriques, nous avons montré que la région la plus critique en termes d’activation se trouve sous les espaceurs de la grille. Nous montrons alors qu’une intégration dite « extension first » est le meilleur compromis pour obtenir de bonnes performances sur des dispositifs fabriqués à faible température. En effet, l’implantation des dopants avant l’épitaxie qui vise à surélever les sources et drains compense l’absence de diffusion à basse température. Ces résultats ont par la suite été étendus pour des dispositifs TriGate et FinFETs sur isolants. Pour la première fois, l’intégration « extension first » a été démontrée pour des N et PFETs d’une technologie 14 nm FDSOI avec des résultats prometteurs en termes de performances. Les résultats obtenus montrent notamment qu’il est possible d’amorphiser partiellement un film très mince avant d’effectuer une recroissance épitaxiale sur une couche dopée. Finalement, une implantation ionique à relativement haute température (jusqu’à 500 °C) a été étudiée afin de doper les accès sans amorphiser totalement le film mince, ce qui est critique dans le cas des dispositifs FDSOI et FinFET. Nous montrons que les niveaux d’activation après implantation sont trop faibles pour obtenir des bonnes performances et que l’implantation ionique « chaude » est prometteuse à condition d’être utilisée avec un autre mécanisme d’activation comme le recuit laser