494,503 research outputs found
Discovering Hierarchical Process Models: an Approach Based on Events Clustering
Process mining is a field of computer science that deals with discovery and
analysis of process models based on automatically generated event logs.
Currently, many companies use this technology for optimization and improving
their processes. However, a discovered process model may be too detailed,
sophisticated and difficult for experts to understand. In this paper, we
consider the problem of discovering a hierarchical business process model from
a low-level event log, i.e., the problem of automatic synthesis of more
readable and understandable process models based on information stored in event
logs of information systems.
Discovery of better structured and more readable process models is
intensively studied in the frame of process mining research from different
perspectives. In this paper, we present an algorithm for discovering
hierarchical process models represented as two-level workflow nets. The
algorithm is based on predefined event ilustering so that the cluster defines a
sub-process corresponding to a high-level transition at the top level of the
net. Unlike existing solutions, our algorithm does not impose restrictions on
the process control flow and allows for concurrency and iteration
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EXTEND-L : an input language for extensible register transfer compilation
This report discusses the model and input language for EXTEND, a synthesis system that permits extensible register transfer synthesis. EXTEND-L fills the need for a language that bridges the gap between existing behavioral input descriptions, which are too abstract, and structural schematics, which cannot capture the high-level behavior. The report first discusses previous work in behavioral synthesis and summarizes the deficiencies of these behavioral specifications. The report then describes the proposed langauge in detail, and concludes with a few examples that show its utility
Hardware synthesis from high-level scenario specifications
PhD ThesisThe behaviour of many systems can be partitioned into scenarios. These facilitate
engineersā understanding of the specifications, and can be composed into efficient
implementations via a form of high-level synthesis. In this work, we focus on highly
concurrent systems, whose scenarios are typically described using concurrency models
such as partial orders, Petri nets and data-flow structures.
In this thesis, we study different aspects of hardware synthesis from high-level
scenario specifications. We propose new formal models to simplify the specification
of concurrent systems, and algorithms for hardware synthesis and verification of the
scenario-based models of such systems. We also propose solutions for mapping scenariobased
systems on silicon and evaluate their efficiency.
Our experiments show that the proposed approaches improve the design of concurrent
systems. The new formalisms can break down complex specifications into
significantly simpler scenarios automatically, and can be used to fully model the dataflow
of operations of reconfigurable event-driven systems. The proposed heuristics for
mapping the scenarios of a system to a digital circuit supports encoding constraints,
unlike existing methods, and can cope with specifications comprising hundreds of
scenarios at the cost of only 5% of area overhead compared to exact algorithms.
These experiments are driven by three case studies: (1) hardware synthesis of control
architectures, e.g. microprocessor control units; (2) acceleration of the ordinal pattern
encoding, i.e. an algorithm for detecting repetitive patterns within data streams; (3) and
acceleration of computational drug discovery, i.e. computation of shortest paths in large
protein-interaction networks.
Our findings are employed to design two prototypes, which have a practical value for
the considered case studies. The ordinal pattern encoding accelerator is asynchronous,
highly resilient to unstable voltage supply, and designed to perform a range of computations
via runtime reconfiguration. The drug discovery accelerator is synchronous, and
up to three orders of magnitude faster than conventional software implementations
Concurrent Design of Embedded Control Software
Embedded software design for mechatronic systems is becoming an increasingly time-consuming and error-prone task. In order to cope with the heterogeneity and complexity, a systematic model-driven design approach is needed, where several parts of the system can be designed concurrently. There is however a trade-off between concurrency efficiency and integration efficiency. In this paper, we present a case study on the development of the embedded control software for a real-world mechatronic system in order to evaluate how we can integrate concurrent and largely independent designed embedded system software parts in an efficient way. The case study was executed using our embedded control system design methodology which employs a concurrent systematic model-based design approach that ensures a concurrent design process, while it still allows a fast integration phase by using automatic code synthesis. The result was a predictable concurrently designed embedded software realization with a short integration time
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EXEL : a language for interactive behavioral synthesis
This paper describes a new input language for behavioral synthesis called EXEL. EXEL is a powerful language that permits the user to specify partially designed structures in the language. It employs a mixed graphic/textual user interface to enhance user interactivity. EXEL's design model is comprehensive: it permits specification of synchronous and asynchronous behavior, and allows specification of general timing constraints. A flexible type construct permits the user to define operators and components to be used in the description. Finally, it simplifies compilation by using a small set of constructs for specifying timing and asynchronouos behavior. The compiler for EXEL runs on SUN-3 workstations and is written in C and SUNVIEW
Realizing live sequence charts in SystemVerilog.
The design of an embedded control system starts with an investigation of properties and behaviors of the process evolving within its environment, and an analysis of the requirement for its safety performance. In early stages, system requirements are often specified as scenarios of behavior using sequence charts for different use cases. This specification must be precise, intuitive and expressive enough to capture different aspects of embedded control systems. As a rather rich and useful extension to the classical message sequence charts, live sequence charts (LSC), which provide a rich collection of constructs for specifying both possible and mandatory behaviors, are very suitable for designing an embedded control system. However, it is not a trivial task to realize a high-level design model in executable program codes effectively and correctly. This paper tackles the challenging task by providing a mapping algorithm to automatically synthesize SystemVerilog programs from given LSC specifications
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BIF : a behavioral intermediate format for high level synthesis
This report describes a new intermediate format for behavioral synthesis systems, based on annotated state tables. It supports user control of the synthesis process by allowing specification of partial design structures, user-bindings and user modification of compiled designs. It is a simple and uniform representation that can be used as an intermediate exchange format for various behavioral synthesis tools. The format captures synchronous and asynchronous behavior, and serves as a good interface to the user by linking behavior and structure at each level of abstraction in the behavioral synthesis process
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