Current Technology for Thermal Protection Systems

Interest in thermal protection systems for high-speed vehicles is increasing because of the stringent requirements of such new projects as the Space Exploration Initiative, the National Aero-Space Plane, and the High-Speed Civil Transport, as well as the needs for improved capabilities in existing thermal protection systems in the Space Shuttle and in turbojet engines. This selection of 13 papers from NASA and industry summarizes the history and operational experience of thermal protection systems utilized in the national space program to date, and also covers recent development efforts in thermal insulation, refractory materials and coatings, actively cooled structures, and two-phase thermal control systems

Evaluation of metal-organic frameworks in electronic devices for gas sensing

Integrating nano-porous metal-organic frameworks (MOFs) in electronic devices such as capacitors, transistor or memristor enables sensing applications for a wide variety of guest molecules. Particularly, the incorporation of thin MOF films in metal-insulator-semiconductor (MIS) capacitor structures allows real-life applications because of its low voltage operation. Additionally, MIS capacitors offer a thorough study of interfacial defects such as interface traps and border traps distributed within the device. In electronic devices, a low concentration of interfacial defects is required to avoid threshold-voltage instabilities. This fact guarantees good stability and performance of electrical devices. This research work provides detailed investigation about charges and defects in MOFs-based MIS capacitors by impedance spectroscopy. Cu3(BTC)2 was coated directly on silicon, and on thermally grown silicon dioxide surfaces in a layer-by-layer fashion. The layer thickness was easily handled by varying the number of spray cycles in the coating process. In addition, Si/SiO2/Al MIS capacitors were investigated for comparison reasons. The successful growth of ultra-thin Cu3(BTC)2 films on silicon substrates was verified via X-ray diffraction (XRD) experiments. The function of MOFs within MIS capacitors was investigated via capacitance-voltage (C-V) and conductance-voltage (G-V) characteristics measured at different frequencies and temperatures. The results show evidence of positive and negative fixed charges in the Cu3(BTC)2 dielectric layer as well as of the presence of border traps which cause hysteresis in the C-V characteristics. Evidence of interface traps is directly observed by the peak on the conductance curve. Analysis of the data demonstrates that ultra-thin Cu3(BTC)2 films prepared without ultrasonication exhibit a relatively low density of border traps (~1011cm-2), interface traps (~1011eV-1cm-2) and time response in the order of µs. Temperature-dependent measurements degrade the electrical quality of the MOFs. The addition of ultrasonication steps on the coating process decreases considerably the density of border traps. Additionally, the layers are more stable under heating experiments, and after cooling they almost recover the initial state. The experimental results show that MOF-based capacitors exhibit interface quality comparable to inorganic materials, making them suitable for sensing applications

Signaling in 3-D integrated circuits, benefits and challenges

Three-dimensional (3-D) or vertical integration is a design and packaging paradigm that can mitigate many of the increasing challenges related to the design of modern integrated systems. 3-D circuits have recently been at the spotlight, since these circuits provide a potent approach to enhance the performance and integrate diverse functions within amulti-plane stack. Clock networks consume a great portion of the power dissipated in a circuit. Therefore, designing a low-power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Synchronization issues can be more challenging for 3-D circuits since a clock path can spread across several planes with different physical and electrical characteristics. Consequently, designing low power clock networks for 3-D circuits is an important issue. Resonant clock networks are considered efficient low-power alternatives to conventional clock distribution schemes. These networks utilize additional inductive circuits to reduce power while delivering a full swing clock signal to the sink nodes. In this research, a design method to apply resonant clocking to synthesized clock trees is proposed. Manufacturing processes for 3-D circuits include some additional steps as compared to standard CMOS processes which makes 3-D circuits more susceptible to manufacturing defects and lowers the overall yield of the bonded 3-D stack. Testing is another complicated task for 3-D ICs, where pre-bond test is a prerequisite. Pre-bond testability, in turn, presents new challenges to 3-D clock network design primarily due to the incomplete clock distribution networks prior to the bonding of the planes. A design methodology of resonant 3-D clock networks that support wireless pre-bond testing is introduced. To efficiently address this issue, inductive links are exploited to wirelessly transmit the clock signal to the disjoint resonant clock networks. The inductors comprising the LC tanks are used as the receiver circuit for the links, essentially eliminating the need for additional circuits and/or interconnect resources during pre-bond test. Recent FPGAs are quite complex circuits which provide reconfigurablity at the cost of lower performance and higher power consumption as compared to ASIC circuits. Exploiting a large number of programmable switches, routing structures are mainly responsible for performance degradation in FPAGs. Employing 3-D technology can providemore efficient switches which drastically improve the performance and reduce the power consumption of the FPGA. RRAM switches are one of the most promising candidates to improve the FPGA routing architecture thanks to their low on-resistance and non-volatility. Along with the configurable switches, buffers are the other important element of the FPGAs routing structure. Different characteristics of RRAM switches change the properties of signal paths in RRAM-based FPGAs. The on resistance of RRAMswitches is considerably lower than CMOS pass gate switches which results in lower RC delay for RRAM-based routing paths. This different nature in critical path and signal delay in turn affect the need for intermediate buffers. Thus the buffer allocation should be reconsidered. In the last part of this research, the effect of intermediate buffers on signal propagation delay is studied and a modified buffer allocation scheme for RRAM-based FPGA routing path is proposed

Design and characterization of BiCMOS mixed-signal circuits and devices for extreme environment applications

State-of-the-art SiGe BiCMOS technologies leverage the maturity of deep-submicron silicon CMOS processing with bandgap-engineered SiGe HBTs in a single platform that is suitable for a wide variety of high performance and highly-integrated applications (e.g., system-on-chip (SOC), system-in-package (SiP)). Due to their bandgap-engineered base, SiGe HBTs are also naturally suited for cryogenic electronics and have the potential to replace the costly de facto technologies of choice (e.g., Gallium-Arsenide (GaAs) and Indium-Phosphide (InP)) in many cryogenic applications such as radio astronomy. This work investigates the response of mixed-signal circuits (both RF and analog circuits) when operating in extreme environments, in particular, at cryogenic temperatures and in radiation-rich environments. The ultimate goal of this work is to attempt to fill the existing gap in knowledge on the cryogenic and radiation response (both single event transients (SETs) and total ionization dose (TID)) of specific RF and analog circuit blocks (i.e., RF switches and voltage references). The design approach for different RF switch topologies and voltage references circuits are presented. Standalone Field Effect Transistors (FET) and SiGe HBTs test structures were also characterized and the results are provided to aid in the analysis and understanding of the underlying mechanisms that impact the circuits' response. Radiation mitigation strategies to counterbalance the damaging effects are investigated. A comprehensive study on the impact of cryogenic temperatures on the RF linearity of SiGe HBTs fabricated in a new 4th-generation, 90 nm SiGe BiCMOS technology is also presented.Ph.D

High efficiency planar microwave antennas assembled using millimetre thick micromachine polymer structures

Communication systems at microwave and millimetre wave regimes require compact broadband high gain antenna devices for a variety of applications, ranging from simple telemetry antennas to sophisticated radar systems. High performance can usually be achieved by fabricating the antenna device onto a substrate with low dielectric constant or recently through micromachining techniques. This thesis presents the design, fabrication, assembly and characterisation of microstrip and CPW fed micromachined aperture coupled single and stacked patch antenna devices. It was found that the micromachining approach can be employed to achieve a low dielectric constant region under the patch which results in suppression of surface waves and hence increasing radiation efficiency and bandwidth. A micromachining method that employs photolithography and metal deposition techniques was developed to produce high efficiency antenna devices. The method is compatible with integration of CMOS chips and filters onto a common substrate. Micromachined polymer rims (SU8 photoresist) was used to create millimetre thick air gaps between the patch and the substrate. The effect of the substrate materials and the dimensions of the SU8 polymer rims on the performance of the antenna devices were studied by numerical simulation using Ansoft HFSS electromagnetic field simulation package. The antenna structures were fabricated in layers and assembled by bonding the micromachined polymer spacers together. Low cost materials like SU8, polyimide and liquid crystal polymer films were used for fabrication and assembly of the antenna devices. A perfect patch antenna device is introduced by replacing the substrate of a conventional patch antenna device with air in order to compare with the micromachined antenna devices. The best antenna parameters for a perfect patch antenna device with air as a substrate medium are ~20% for bandwidth and 9.75 dBi for antenna gain with a radiation efficiency of 99.8%. In comparison, the best antenna gain for the simple micromachined patch antenna device was determined to be ~8.6 dBi. The bandwidth was ~20 % for a microstrip fed device with a single patch; it was ~40 % for stacked patch devices. The best bandwidth and gain of 6.58 GHz (50.5%) and 11.2 dBi were obtained for a micromachined sub-array antenna device. The simulation results show that the efficiency of the antenna devices is above 95 %. Finally, a novel high gain planar antenna using a frequency selective surface (FSS) was studied for operation at ~60 GHz frequency. The simulation results show that the novel antenna device has a substantial directivity of around 25 dBi that is required for the emerging WLAN communications at the 60 GHz frequency band

SELF-ORGANIZATION IN MICROWAVE FILAMENTARY DISCHARGES

We studied the self organising phenomena im filamntary microwave discharge at various pressures and excitation types

Silicon Integrated Arrays: From Microwave to IR

Integrated chips have enabled realization and mass production of complex systems in a small form factor. Through process miniaturization many novel applications in silicon photonics and electronic systems have been enabled. In this thesis I have provided several examples of innovations that are only enabled by integration. I have also demonstrated how electronics and photonics circuits can complement each other to achieve a system with superior performance.</p