낸드플래시 메모리 셀 간의 문턱전압 변화를 반영한 센싱 시스템 모델링 및 검증 방법

학위논문 (석사) -- 서울대학교 대학원 : 공학전문대학원 응용공학과, 2021. 2. 김재하.The sensing system in NAND flash memories is a complex mixed-signal circuit consisting of a large-scale cell array, wordline decoders, page buffers, analog/digital bit-counters, and digital sequence controllers. This paper proposes a model and simulation framework that can assess the effectiveness of various incremental/adaptive algorithms used by digital controllers for the read, program, and erase operations, while simulating the progression of individual cell threshold voltages (Vth) and modeling the detailed analog characteristics of the page buffers. The proposed model is written entirely in SystemVerilog, and its analog parts are described using the XMODEL primitives, which enable efficient and event-driven simulation of analog circuits. The proposed model can simulate a 40μs-long incremental step pulse programming (ISPP) sequence with the maximum loop iteration count of 4 on a 12K-bit block of single-level cells (SLC) in less than 2 minutes, and can assess the trade-offs between the programming speed and reliability as a function of the pulse step size and the impacts of the page buffers sensing time on the final cell Vth distribution.NAND 플래시 메모리의 센싱 시스템은 대용량의 데이터를 저장할 수 있는 셀 어레이와 이를 구동시키기 위한 워드 라인 디코더, 페이지 버퍼, 아날로그 / 디지털 비트 카운터 및 디지털 시퀀스 컨트롤러로 구성된 복잡한 혼성신호 회로이다. 본 연구에서는 개별 셀의 초기 조건과 특성에 따라 서로 다른 양상을 보이는 문턱 전압 (Vth)의 변화를 반영할 수 있으며, 페이지 버퍼의 특성을 포함한 상세한 아날로그 동작들의 모델링하여 디지털 컨트롤러가 읽기, 프로그램 및 삭제 작업에 사용하는 다양한 알고리즘의 효율성을 평가할 수있는 모델 및 시뮬레이션 프레임 워크를 제안한다. 제안하는 모델은 디지털과 아날로그로 나뉘어진 검증환경이 아닌 하나의 통합된 SystemVerilog기반으로 작성되었으며, 특히 XMODEL 프리미티브를 사용하여 아날로그 회로의 이벤트 기반 시뮬레이션을 통해 효율적인 검증이 가능하게 되었다. 해당 시스템 모델을 기반으로 12K 비트의 단일 레벨 셀 (SLC) 블록에서 최대 루프 반복 횟수가 4 회인 40μs 길이의 ISPP (Incremental Step Pulse Programming) 동작을 2 분 이내에 시뮬레이션 할 수 있었다. 또한, 검증과정을 통해 얻게 되는 개별 셀 Vth 분포 분석을 통해서 프로그래밍 속도와 신뢰성 사이의 관계를 펄스 스텝 크기의 함수로서 표현할 수 있었으며, 페이지 버퍼의 센싱 시간 조절을 통한 최종 셀 Vth 분포의 중심치에 대한 영향에 대해서도 검증가능하다.Chapter 1. Introduction 1 1.1. Study Background 1 1.2. Thesis Organization 3 Chapter 2. Background 4 2.1. NAND Flash Memory Architecture and Its Operations 4 2.2. Previous Works 8 Chapter 3. Proposed SystemVerilog Model of NAND Flash Memory Sensing System 11 3.1. Cell Array Model 12 3.2. Page Buffer Model 15 3.3. Analog Bit-Counter Model 19 3.4. Digital System Model 22 Chapter 4. Experimental Results 23 4.1. SLC Program with Different ISPP Steps 25 4.2. SLC Program with Different Sensing Times 28 Chapter 5. Conclusions 30 Bibliography 31 Appendix 33 Abstract in Korean 40Maste

Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers

NAND flash memories are becoming the predominant technology in the implementation of mass storage systems for both embedded and high-performance applications. However, when considering data and code storage in non-volatile memories (NVMs), such as NAND flash memories, reliability and performance be- come a serious concern for systems' designer. Designing NAND flash based systems based on worst-case scenarios leads to waste of resources in terms of performance, power consumption, and storage capacity. This is clearly in contrast with the request for run-time reconfigurability, adaptivity, and resource optimiza- tion in nowadays computing systems. There is a clear trend toward supporting differentiated access modes in flash memory controllers, each one setting a differentiated trade-off point in the performance-reliability optimization space. This is supported by the possibility of tuning the NAND flash memory performance, reli- ability and power consumption acting on several tuning knobs such as the flash programming algorithm and the flash error correcting code. However, to successfully exploit these degrees of freedom, it is mandatory to clearly understand the effect the combined tuning of these parameters have on the full NVM sub-system. This paper performs a comprehensive quantitative analysis of the benefits provided by the run-time reconfigurability of an MLC NAND flash controller through the combined effect of an adaptable memory programming circuitry coupled with run-time adaptation of the ECC correction capability. The full non- volatile memory (NVM) sub-system is taken into account, starting from the characterization of the low level circuitry to the effect of the adaptation on a wide set of realistic benchmarks in order to provide the readers a clear figure of the benefit this combined adaptation would provide at the system leve

Design of an Integrated Acceleration Acquisition Subsystem to Satisfy High-Speed and Low-Area Requirements for CubeSats

Cal Poly San Luis Obispo’s PolySat team is designing the Multipurpose Orbital Spring Ejection System (MOSES) in order to record acceleration data during the launch of CubeSats as well as to provide GPS coordinates to locate the position of CubeSats once they are injected into orbit. This work focuses on the design and development of the acceleration data acquisition (DAQ) subsystem of MOSES. This subsystem is designed around the need for a high-speed sampling system of at least 200 kHz across four channels of data, plus low-area limitations in the MOSES form factor which is roughly half the size of a standard CubeSat. To address these specifications, the design explores system implementation around a Xilinx Artix-7 FPGA with a built-in analog-to-digital converter and a custom hardware solution

A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories

In spite of the mature cell structure, the memory controller architecture of Multi-level cell (MLC) NAND Flash memories is evolving fast in an attempt to improve the uncorrected/miscorrected bit error rate (UBER) and to provide a more flexible usage model where the performance-reliability trade-off point can be adjusted at runtime. However, optimization techniques in the memory controller architecture cannot avoid a strict trade-off between UBER and read throughput. In this paper, we show that co-optimizing ECC architecture configuration in the memory controller with program algorithm selection at the technology layer, a more flexible memory sub-system arises, which is capable of unprecedented trade-offs points between performance and reliability

머신 러닝 기반의 낸드 플래시 칩 eFuse 구성 생성 자동화 방법론

학위논문(석사)--서울대학교 대학원 :공과대학 컴퓨터공학부,2019. 8. 유승주.Post fabrication process is becoming more and more important as memory technology becomes complex, in the bid to satisfy target performance and yield across diverse business domains, such as servers, PCs, automotive, mobiles, and embedded devices, etc. Electronic fuse adjustment (eFuse optimization and trimming) is a traditional method used in the post fabrication processing of memory chips. Engineers adjust eFuse to compensate for wafer inter-chip variations or guarantee the operating characteristics, such as reliability, latency, power consumption, and I/O bandwidth. These require highly skilled expert engineers and yet take significant time. This paper proposes a novel machine learning-based method of automatic eFuse configuration to meet the target NAND flash operating characteristics. The proposed techniques can maximally reduce the expert engineers workload. The techniques consist of two steps: initial eFuse generation and eFuse optimization. In the first step, we apply the variational autoencoder (VAE) method to generate an initial eFuse configuration that will probably satisfy the target characteristics. In the second step, we apply the genetic algorithm (GA), which attempts to improve the initial eFuse configuration and finally achieve the target operating characteristics. We evaluate the proposed techniques with Samsung 64-Stacked vertical NAND (VNAND) in mass production. The automatic eFuse configuration takes only two days to complete the implementation.메모리 공정 기술이 발전하고 비즈니스 시장이 다양해 짐에 따라 웨이퍼 수율을 높이고 비즈니스 특성 목표를 만족하기 위한 후 공정 과정이 매우 중요해 지고 있다. 전기적 퓨즈 조절 방식(이-퓨즈 최적화 및 트림)은 메모리 칩 후 공정 과정에서 사용되는 전통적인 방식이다. 엔지니어는 이-퓨즈 조절을 통해 웨이퍼 상의 칩들 간의 초기 특성의 변화를 보상하거나, 신뢰성, 레이턴시, 파워 소모, 그리고 I/O 대역폭 등의 칩 목표 특성을 보장한다. 이-퓨즈 조절 업무는 다수의 숙련된 엔지니어가 필요하고 또한 상당히 많은 시간을 소모한다. 본 논문에서는 낸드 플래시 칩의 동작 특성 목표를 얻기 위한 기계 학습 기반의 이-퓨즈 자동 생성 기술을 제안하고, 해당 기술은 엔지니어의 작업시간을 획기적으로 단축시킬 수 있다. 논문의 기술은 두 단계로 구성 된다. 첫 번째 단계에서는 variational autoencoder (VAE) 기술을 적용하여 목표하는 동작 특성을 만족시키는 초기 이-퓨즈 구성을 생성한다. 두 번째 단계에서는 유전 알고리즘을 적용하여 초기 생성된 이-퓨즈 구성에 대하여 목표하는 성능 특성과의 정합성을 추가로 개선하여 최종적으로 목표하는 성능 특성을 얻는다. 논문의 평가는 실제 양산중인 삼성 64단 브이낸드 제품을 이용하여 진행하였다. 논문의 이-퓨즈 자동화 생성 기술은 2일 이내의 구현 시간만이 소요된다.Contents I. Introduction..........................................................................1 II. Background..........................................................................4 2.1. NAND Flash Block Architecture..................................................4 2.2. NAND Cell Vth Distribution........................................................5 2.3. eFuse Operation of NAND Flash Chip.......................................6 III. Basic Idea and Background...............................................7 3.1. Basic Idea.......................................................................................7 3.2. Background: Variational Autoencoder........................................10 IV. Initial eFuse Generation: VAE-Based Dual Network....14 V. eFuse Optimization: Genetic Algorithm..........................17 VI. Experimental Results.........................................................21 6.1. Experimental Setup......................................................................21 6.2. Initial eFuse Generation Results................................................23 6.3. eFuse Optimization Results........................................................26 6.4. Discussion.....................................................................................29 VII. Related Work..................................................................31 VIII. Conclusion.......................................................................33Maste

Integrated Circuits for Programming Flash Memories in Portable Applications

Smart devices such as smart grids, smart home devices, etc. are infrastructure systems that connect the world around us more than before. These devices can communicate with each other and help us manage our environment. This concept is called the Internet of Things (IoT). Not many smart nodes exist that are both low-power and programmable. Floating-gate (FG) transistors could be used to create adaptive sensor nodes by providing programmable bias currents. FG transistors are mostly used in digital applications like Flash memories. However, FG transistors can be used in analog applications, too. Unfortunately, due to the expensive infrastructure required for programming these transistors, they have not been economical to be used in portable applications. In this work, we present low-power approaches to programming FG transistors which make them a good candidate to be employed in future wireless sensor nodes and portable systems. First, we focus on the design of low-power circuits which can be used in programming the FG transistors such as high-voltage charge pumps, low-drop-out regulators, and voltage reference cells. Then, to achieve the goal of reducing the power consumption in programmable sensor nodes and reducing the programming infrastructure, we present a method to program FG transistors using negative voltages. We also present charge-pump structures to generate the necessary negative voltages for programming in this new configuration