To Develop and Implement Low Power, High Speed VLSI for Processing Signals using Multirate Techniques

Multirate technique is necessary for systems with different input and output sampling rates. Recent advances in mobile computing and communication applications demand low power and high speed VLSI DSP systems [4]. This Paper presents Multirate modules used for filtering to provide signal processing in wireless communication system. Many architecture developed for the design of low complexity, bit parallel Multiple Constant Multiplications operation which dominates the complexity of DSP systems. However, major drawbacks of present approaches are either too costly or not efficient enough. On the other hand, MCM and digit-serial adder offer alternative low complexity designs, since digit-serial architecture occupy less area and are independent of the data word length [1][10]. Multiple Constant Multiplications is efficient way to reduce the number of addition and subtraction in polyphase filter implementation. This Multirate design methodology is systematic and applicable to many problems. In this paper, attention has given to the MCM & digit serial architecture with shifting and adding techniques that offers alternative low complexity in operations. This paper also focused on Multirate Signal Processing Modules using Voltage and Technology scaling. Reduction of power consumption is important for VLSI system and also it becomes one of the most critical design parameter. Transistorized Multirate module which has full custom design with different circuit topology and optimization level simulated on cadence platform. Multirate modules are used AMI 0.6 um, TSMC 0.35 um, and TSMC 0.25 um technologies for different voltage scaling. The presented methodology provides a systematic way to derive circuit technique for high speed operation at a low supply voltage. Multirate polyphase interpolator and decimator are also designed and optimized at architectural level in order to analyze the terms power consumption, area and speed. DOI: 10.17762/ijritcc2321-8169.150314

Concepts for on-board satellite image registration. Volume 3: Impact of VLSI/VHSIC on satellite on-board signal processing

Anticipated major advances in integrated circuit technology in the near future are described as well as their impact on satellite onboard signal processing systems. Dramatic improvements in chip density, speed, power consumption, and system reliability are expected from very large scale integration. Improvements are expected from very large scale integration enable more intelligence to be placed on remote sensing platforms in space, meeting the goals of NASA's information adaptive system concept, a major component of the NASA End-to-End Data System program. A forecast of VLSI technological advances is presented, including a description of the Defense Department's very high speed integrated circuit program, a seven-year research and development effort

A fast carry binary adder

This thesis describes the adder to be used with the Galaxy computer, which is to be constructed at Oregon State University. The need for faster, more reliable adders is discussed along with previous adder designs related to the Galaxy Fast Carry Adder. Both the logical design and circuit design of the Galaxy Fast Carry Adder are discussed. Operating speed measurements for a 3 bit adder are presented and used to predict operating speeds of a 49 bit adder. Reliability considerations are discussed, and a set of worst case resistor value calculations is included as an appendix. The use of the adder circuit in the Galaxy computer is also discussed

Harnessing resilience: biased voltage overscaling for probabilistic signal processing

A central component of modern computing is the idea that computation requires determinism. Contrary to this belief, the primary contribution of this work shows that useful computation can be accomplished in an error-prone fashion. Focusing on low-power computing and the increasing push toward energy conservation, the work seeks to sacrifice accuracy in exchange for energy savings. Probabilistic computing forms the basis for this error-prone computation by diverging from the requirement of determinism and allowing for randomness within computing. Implemented as probabilistic CMOS (PCMOS), the approach realizes enormous energy sav- ings in applications that require probability at an algorithmic level. Extending probabilistic computing to applications that are inherently deterministic, the biased voltage overscaling (BIVOS) technique presented here constrains the randomness introduced through PCMOS. Doing so, BIVOS is able to limit the magnitude of any resulting deviations and realizes energy savings with minimal impact to application quality. Implemented for a ripple-carry adder, array multiplier, and finite-impulse-response (FIR) filter; a BIVOS solution substantially reduces energy consumption and does so with im- proved error rates compared to an energy equivalent reduced-precision solution. When applied to H.264 video decoding, a BIVOS solution is able to achieve a 33.9% reduction in energy consumption while maintaining a peak-signal-to-noise ratio of 35.0dB (compared to 14.3dB for a comparable reduced-precision solution). While the work presented here focuses on a specific technology, the technique realized through BIVOS has far broader implications. It is the departure from the conventional mindset that useful computation requires determinism that represents the primary innovation of this work. With applicability to emerging and yet to be discovered technologies, BIVOS has the potential to contribute to computing in a variety of fashions.PhDCommittee Chair: Anderson, David; Committee Member: Conte, Thomas; Committee Member: Ferri, Bonnie; Committee Member: Hasler, Paul; Committee Member: Mooney, Vincen

Optimum logic design for a fast parallel multiplier

This thesis discusses a method of fast multiplication by parallel addition of summands. A logical element that performs this parallel addition is defined, and examples of the element realized with threshold logic are shown. Relations between the type of logical element used, and the speed and cost of the multiplier are discussed. The optimum type of logical element is defined, and two examples of a multiplier using this optimum element are discussed. By assuming some hypothetical propagation times for the various elements, a multiply time of 500 ns is predicted for an eighty-bit multiplier

Leading Guard Digits in Finite-Precision Redundant Representations

Redundant number representations are generally used to allow constant time additions, based on the fact that only bounded carry-ripples take place. But, carries may ripple out into positions which may not be needed to represent the final value of the result and, thus, a certain amount of leading guard digits are needed to correctly determine the result. Also, when cancellation during subtractions occurs, there may be nonzero digits in positions not needed to represent the result of the calculation. It is shown here that, for normal redundant digit sets with radix greater than two, a single guard digit is sufficient to determine the value of such an arbitrary length prefix of leading nonzero digits. This is also the case for the unsigned carry-save representation, whereas two guard digits are sufficient, and may be necessary, for additions in the binary signed-digit and 2's complement carry-save representations. Thus, only the guard digits need to be retained during sequences of additions and subtractions. At suitable points, the guard digits may then be converted into a single digit, representing the complete prefix

Near-term hybrid vehicle program, phase 1. Appendix B: Design trade-off studies report. Volume 2: Supplement to design trade-off studies

Results of studies leading to the preliminary design of a hybrid passenger vehicle which is projected to have the maximum potential for reducing petroleum consumption in the near term are presented. Heat engine/electric hybrid vehicle tradeoffs, assessment of battery power source, and weight and cost analysis of key components are among the topics covered. Performance of auxiliary equipment, such as power steering, power brakes, air conditioning, lighting and electrical accessories, heating and ventilation is discussed along with the selection of preferred passenger compartment heating procedure for the hybrid vehicle. Waste heat from the engine, thermal energy storage, and an auxiliary burner are among the approaches considered

Space Communications: Theory and Applications. Volume 3: Information Processing and Advanced Techniques. A Bibliography, 1958 - 1963

Annotated bibliography on information processing and advanced communication techniques - theory and applications of space communication

Cumulative index to NASA Tech Briefs, 1963-1965

Annotated bibliography of NASA technical briefs on electrical, energy sources, materials, life sciences, and mechanical informatio