A high-Q second-order all-pass delay network in CMOS

Analogue signal processing (ASP) is a promising alternative to DSP techniques in future telecommunication and data  processing  solutions.  Second‐order  all‐pass  delay  networks  –  the  building  blocks  of  ASPs  –  are  currently  primarily  implemented in off‐chip planar media, which is unsuited for volume production. In this work, a novel on‐chip CMOS second‐order all‐pass network is proposed that includes a post‐production tuning mechanism. It is shown that automated tuning with a genetic local optimizer can compensate for CMOS process variation and parasitics, which make physical realization otherwise infeasible. Measurements indicate a post‐tuning bandwidth of 280 MHz, peak‐to‐nominal delay variation of 10 ns and  magnitude  variation  of  3.1  dB.  This  is  the  first  time  that  measurement  results  have  been  reported  for  an  active  inductorless on‐chip second‐order all‐pass network with a delay Q‐value larger than 1.http://digital-library.theiet.org/content/journals/iet-cdshj2018Electrical, Electronic and Computer Engineerin

Synthesis and monolithic integration of analogue signal processing networks

Data traffic of future 5G telecommunication systems is projected to increase 10 000-fold compared to current rates. 5G fronthaul links are therefore expected to operate in the mm-wave spectrum with some preliminary International Telecommunication Union specifications set for the 71-76 and 81-86 GHz bands. Processing 5 GHz as a single contiguous band in real-time, using existing digital signal processing (DSP) systems, is exceedingly challenging. A similar challenge exists in radio astronomy, with the Square Kilometer Array project expecting data throughput rates of 15 Tbits/s at its completion. Speed improvements on existing state-of-the-art DSPs of 2-3 orders of magnitude are therefore required to meet future demands. One possible mitigating approach to processing wideband data in real-time is to replace some DSP blocks with analog signal processing (ASP) equivalents, since analogue devices outperform their digital counterparts in terms of cost, power consumption and the maximum attainable bandwidth. The fundamental building block of any ASP is an all-pass network of prescribed response, which can always be synthesized by cascaded first- and second-order all-pass sections (with two cascaded first-order sections being a special case of the latter). The monolithic integration of all-pass networks in commercial CMOS and BiCMOS technology nodes is a key consideration for commercial adaptation of ASPs, since it supports mass production at reduced costs and operating power requirements, making the ASP approach feasible. However, this integration has presented a number of yet unsolved challenges. Firstly, the state-of-the-art methods for synthesizing quasi-arbitrary group delay functions using all-pass elements lack a theoretical synthesis procedure that guarantees minimum-order networks. In this work an analytically-based solution to the synthesis problem is presented that produces an all-pass network with a response approximating the required group delay to within an arbitrary minimax error. This method is shown to work for any physical realization of second-order all-pass elements, is guaranteed to converge to a global optimum solution without any choice of seed values as an input, and allows synthesis of pre-defined networks described either analytically or numerically. Secondly, second-order all-pass networks are currently primarily implemented in off-chip planar media, which is unsuited for high volume production. Component sensitivity, process tolerances and on-chip parasitics often make proposed on-chip designs impractical. Consequently, to date, no measured results of a dispersive on-chip second-order all-pass network suitable for ASP applications (delay Q-value (QD) larger than 1) have been presented in either CMOS or BiCMOS technology nodes. In this work, the first ever on-chip CMOS second-order all-pass network is proposed with a measured QD-value larger than 1. Measurements indicate a post-tuning bandwidth of 280 MHz, peak-to-nominal delay variation of 10 ns, QD-value of 1.15 and magnitude variation of 3.1 dB. An active on-chip mm-wave second-order all-pass network is further demonstrated in a 130 nm SiGe BiCMOS technology node with a bandwidth of 40 GHz, peak-to-nominal delay of 62 ps, QD-value of 3.6 and a magnitude ripple of 1.4 dB. This is the first time that measurement results of a mm-wave bandwidth second-order all-pass network have been reported. This work therefore presents the first step to monolithically integrating ASP solutions to conventional DSP problems, thereby enabling ultra-wideband signal processing on-chip in commercial technology nodes.Thesis (PhD)--University of Pretoria, 2018.Square Kilometer Array (SKA) project - postgraduate scholarshipElectrical, Electronic and Computer EngineeringPhDUnrestricte

Tunable n-path notch filters for blocker suppression: modeling and verification

N-path switched-RC circuits can realize filters with very high linearity and compression point while they are tunable by a clock frequency. In this paper, both differential and single-ended N-path notch filters are modeled and analyzed. Closed-form equations provide design equations for the main filtering characteristics and nonidealities such as: harmonic mixing, switch resistance, mismatch and phase imbalance, clock rise and fall times, noise, and insertion loss. Both an eight-path single-ended and differential notch filter are implemented in 65-nm CMOS technology. The notch center frequency, which is determined by the switching frequency, is tunable from 0.1 to 1.2 GHz. In a 50- environment, the N-path filters provide power matching in the passband with an insertion loss of 1.4–2.8 dB. The rejection at the notch frequency is 21–24 dB,P1 db> + 2 dBm, and IIP3 > + 17 dBm

Microwave and RF Applications for Micro-resonator based Frequency Combs

Photonic integrated circuits that exploit nonlinear optics in order to generate and process signals all-optically have achieved performance far superior to that possible electronically - particularly with respect to speed. We review the recent achievements based in new CMOS-compatible platforms that are better suited than SOI for nonlinear optics, focusing on radio frequency (RF) and microwave based applications that exploit micro-resonator based frequency combs. We highlight their potential as well as the challenges to achieving practical solutions for many key applications. These material systems have opened up many new capabilities such as on-chip optical frequency comb generation and ultrafast optical pulse generation and measurement. We review recent work on a photonic RF Hilbert transformer for broadband microwave in-phase and quadrature-phase generation based on an integrated frequency optical comb. The comb is generated using a nonlinear microring resonator based on a CMOS compatible, high-index contrast, doped-silica glass platform. The high quality and large frequency spacing of the comb enables filters with up to 20 taps, allowing us to demonstrate a quadrature filter with more than a 5-octave (3 dB) bandwidth and an almost uniform phase response.Comment: 10 pages, 6 figures, 68 references. arXiv admin note: substantial text overlap with arXiv:1512.0174

Electronically Tunable Resistorless Mixed Mode Biquad Filters

This paper presents a new realization of elec¬tronically tunable mixed mode (including transadmittance- and voltage-modes) biquad filter with single input, three outputs or three inputs, single output using voltage differ-encing transconductance amplifier (VDTA), a recently introduced active element. It can simultaneously realize standard filtering signals: low-pass, band-pass and high-pass or by selecting input terminals, it can realize all five different filtering signals: low-pass, band-pass, high-pass, band-stop and all-pass. The proposed filter circuit offers the following attractive feature: no requirement of invert-ing type input signal which is require no addition circuit, critical component matching conditions are not required in the design, the circuit parameters ω0 and Q can be set orthogonally or independently through adjusting the bias currents of the VDTAs, the proposed circuit employs two active and minimum numbers of passive components. Fur-thermore, this filter was investigated from the point of view of limited frequency range, stability conditions, effects of parasitic elements and effects of non-ideal and sensitivity. Thus, taking these effects and conditions into considera¬tion, working conditions and boundaries of this filter are determined. We also performed Monte Carlo, THD and noise analyses. Simulation results are given to confirm theoretical analyses

A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.A fully-integrated reconfigurable dual-band (760-960 MHz and 2.4-2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PA's operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by x3.24 and x1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by x2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.Peer reviewe

A 0.18μm CMOS 300MHz Current-Mode LF Seventh-order Linear Phase Filter for Hard Disk Read Channels

“This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”A 300MHz CMOS seventh-order linear phase gm-C filter based on a current-mode multiple loop feedback (MLF) leap-frog (LF) structure is realized. The filter is implemented using a fully-differential linear operational transconductance amplifier (OTA) based on a source degeneration topology. PSpice simulations using a standard TSMC 0.18μm CMOS process with 2.5V power supply have shown that the cut-off frequency of the filter can be tuned from 260MHz to 320MHz and dynamic range is about 66dB. Group delay ripple is approximately 4.5% over the whole tuning range and maximum power consumption is 210mW