The Timing of Reward-Seeking Action Tracks Visually-Cued Theta Oscillations in Primary Visual Cortex

An emerging body of work challenges the view that primary visual cortex (V1) represents the visual world faithfully. Theta oscillations in the local field potential (LFP) of V1 have been found to convey temporal expectations and, specifically, to express the delay between a visual stimulus and the reward that it portends. We extend this work by showing how these oscillatory states in male, wild-type rats can even relate to the timing of a visually cued reward-seeking behavior. In particular, we show that, with training, high precision and accuracy in behavioral timing tracks the power of these oscillations and the time of action execution covaries with their duration. These LFP oscillations are also intimately related to spiking responses at the single-unit level, which themselves carry predictive timing information. Together, these observations extend our understanding of the role of cortical oscillations in timing generally and the role of V1 in the timing of visually cued behaviors specifically.Fil: Levy, Joshua M.. University Johns Hopkins; Estados UnidosFil: Zold, Camila Lidia. Consejo Nacional de Investigaciones Científicas y Técnicas. Oficina de Coordinación Administrativa Houssay. Instituto de Fisiología y Biofísica Bernardo Houssay. Universidad de Buenos Aires. Facultad de Medicina. Instituto de Fisiología y Biofísica Bernardo Houssay; ArgentinaFil: Namboodiri, Vijay Mohan K.. University of North Carolina; Estados UnidosFil: Hussain Shuler, Marshall G. University Johns Hopkins; Estados Unido

Exploiting Inter- and Intra-Memory Asymmetries for Data Mapping in Hybrid Tiered-Memories

Modern computing systems are embracing hybrid memory comprising of DRAM and non-volatile memory (NVM) to combine the best properties of both memory technologies, achieving low latency, high reliability, and high density. A prominent characteristic of DRAM-NVM hybrid memory is that it has NVM access latency much higher than DRAM access latency. We call this inter-memory asymmetry. We observe that parasitic components on a long bitline are a major source of high latency in both DRAM and NVM, and a significant factor contributing to high-voltage operations in NVM, which impact their reliability. We propose an architectural change, where each long bitline in DRAM and NVM is split into two segments by an isolation transistor. One segment can be accessed with lower latency and operating voltage than the other. By introducing tiers, we enable non-uniform accesses within each memory type (which we call intra-memory asymmetry), leading to performance and reliability trade-offs in DRAM-NVM hybrid memory. We extend existing NVM-DRAM OS in three ways. First, we exploit both inter- and intra-memory asymmetries to allocate and migrate memory pages between the tiers in DRAM and NVM. Second, we improve the OS's page allocation decisions by predicting the access intensity of a newly-referenced memory page in a program and placing it to a matching tier during its initial allocation. This minimizes page migrations during program execution, lowering the performance overhead. Third, we propose a solution to migrate pages between the tiers of the same memory without transferring data over the memory channel, minimizing channel occupancy and improving performance. Our overall approach, which we call MNEME, to enable and exploit asymmetries in DRAM-NVM hybrid tiered memory improves both performance and reliability for both single-core and multi-programmed workloads.Comment: 15 pages, 29 figures, accepted at ACM SIGPLAN International Symposium on Memory Managemen

Analysis and design of digital output interface devices for gas turbine electronic controls

A trade study was performed on twenty-one digital output interface schemes for gas turbine electronic controls to select the most promising scheme based on criteria of reliability, performance, cost, and sampling requirements. The most promising scheme, a digital effector with optical feedback of the fuel metering valve position, was designed

Leading Indicators of Inflation for Brazil

The goal of this project is to construct leading indicators that anticipate inflation cycle turning points on a real time monitoring basis. As a first step, turning points of the IPCA inflation are determined using a periodic stochastic Markov switching model. These turning points are the event timing that the leading indicators should anticipate. A dynamic factor model is then used to extract common cyclical movements in a set of variables that display predictive content for inflation. The leading indicators are designed to serve as practical tools to assist real-time monitoring of monetary policy on a month-to-month basis. Thus, the indicators are built and ranked according to their out-of-sample forecasting performance. The leading indicators are found to be an informative tool for signaling future phases of the inflation cycle out-of-sample, even in real time when only preliminary and unrevised data are available.

Implementable Wireless Access for B3G Networks - III: Complexity Reducing Transceiver Structures

This article presents a comprehensive overview of some of the research conducted within Mobile VCE’s Core Wireless Access Research Programme,1 a key focus of which has naturally been on MIMO transceivers. The series of articles offers a coherent view of how the work was structured and comprises a compilation of material that has been presented in detail elsewhere (see references within the article). In this article MIMO channel measurements, analysis, and modeling, which were presented previously in the first article in this series of four, are utilized to develop compact and distributed antenna arrays. Parallel activities led to research into low-complexity MIMO single-user spacetime coding techniques, as well as SISO and MIMO multi-user CDMA-based transceivers for B3G systems. As well as feeding into the industry’s in-house research program, significant extensions of this work are now in hand, within Mobile VCE’s own core activity, aiming toward securing major improvements in delivery efficiency in future wireless systems through crosslayer operation