Extending systems-on-chip to the third dimension : performance, cost and technological tradeoffs.

Because of the today's market demand for high-performance, high-density portable hand-held applications, electronic system design technology has shifted the focus from 2-D planar SoC single-chip solutions to different alternative options as tiled silicon and single-level embedded modules as well as 3-D integration. Among the various choices, finding an optimal solution for system implementation dealt usually with cost, performance and other technological trade-off analysis at the system conceptual level. It has been identified that the decisions made within the first 20% of the total design cycle time will ultimately result up to 80% of the final product cost. In this paper, we discuss appropriate and realistic metric for performance and cost trade-off analysis both at system conceptual level (up-front in the design phase) and at implementation phase for verification in the three-dimensional integration. In order to validate the methodology, two ubiquitous electronic systems are analyzed under various implementation schemes and discuss the pros and cons of each of them

Accurate a priori signal integrity estimation using a multilevel dynamic interconnect model for deep submicron VLSI design.

A multilevel dynamic interconnect model was derived for accurate a priori signal integrity estimates. Cross-talk and delay estimations over interconnects in deep submicron technology were analyzed systematically using this model. Good accuracy and excellent time-efficiency were found compared with electromagnetic simulations. We aim to build a dynamic interconnect library with this model to facilitate the interconnect issues for future VLSI design

Back-annotation for interactive data path synthesis

In order to take into account physical design effects, a designer needs a feedback mechanism during interactive data path synthesis. In this paper, we propose a hypergraph model and a back-annotation algorithm which provide a feedback mechanism for back-annotation from physical designs to behavioral descriptions. Given a control data flow graph and its structural design, this back-annotation technique cannot only evaluate the design quality but can also feedback the delay to each edge and node in the graph. Therefore, a designer can identify the critical paths and improve the design. The hypergraph model and the back-annotation algorithm allow us to bridge the gap between the behavioral description and the physical design

Layout area models for high-level synthesis

Traditionally, the common cost functions, the number of functional units, registers and selector inputs, are used in high level synthesis as quality measures. However, these traditional design quality measures may not reflect the real physical design. To establish quality measures based on the physical designs, we propose layout estimation models for two commonly used data path and control layout architectures. The results show that quality measures deriving from our models give an accurate prediction of the final layout. The results also show that traditional cost functions are not good indicators for optimization in high level synthesis

A global wire planning scheme for Network-on-Chip.

As technology scales down, the interconnect for on-chip global communication becomes the delay bottleneck. In order to provide well-controlled global wire delay and efficient global communication, a packet switched Network-on-Chip (NoC) architecture was proposed by different authors. In this paper, the NoC system parameters constrained by the interconnections are studied. Predictions on scaled system parameters such as clock frequency, resource size, global communication bandwidth and inter-resource delay are made for future technologies. Based on these parameters, a global wire planning scheme is proposed

Macromodeling strategy for digital devices and interconnects

International audienceThis paper proposes a macromodeling approach for the simulation of digital interconnected systems. Such an approach is based on a set of macromodels describing IC ports, IC packages and multiconductor interconnect structures in standard circuit simulators, like SPICE. We illustrate the features of the macromodels and we demonstrate the proposed approach on a realistic simulation problem