Dielectric breakdown II: Related projects at the University of Twente

In this paper an overview is given of the related activities in our group of the University of Twente. These are on thin film transistors with the inherent difficulty of making a gate dielectric at low temperature, on thin dielectrics for EEPROM devices with well-known requirements with respect to charge retention and endurance and, finally, on thin film diodes in displays with unexpected breakdown properties

Growth and Oxidation of Graphene and Two-Dimensional Materials for Flexible Electronic Applications

The non-volatile storage of information is becoming increasingly important in our data-driven society. Limitations in conventional devices are driving the research and development of incorporating new materials into conventional device architectures to improve performance, as well as developing an array of emerging memory technologies based on entirely new physical processes. The discovery of graphene allowed for developing new approaches to these problems, both itself and as part of the larger, and ever-expanding family of 2D materials. In this thesis the growth and oxidation of these materials is investigated for implementing into such devices, exploiting some of the unique properties of 2D materials including atomic thinness, mechanical flexibility and tune-ability through chemical modification - to meet some challenges facing the community. This begins with the growth of graphene by chemical vapour deposition for a high quality flexible electrode material, followed by oxidation of graphene for use in resistive memory devices. The theme of oxidation is then extended to another 2D material, HfS2, which is selectively oxidised for use as high-k dielectric in Van der Waals heterostructures for FETs and resistive memory devices. Lastly, a technique for fabrication of graphene-based devices directly on the copper growth substrate is demonstrated for use in flexible devices for sensing touch and humidity

New processing techniques for large-area electronics

Recent advancements in the semiconductor industry have been driven by the extreme downscaling of device dimensions enabled by innovative photolithography methods. However, such nano-scale patterning technologies are impractical for large-area electronics primarily due to extremely high cost and incompatibility with large-area processing. Therefore, alternative techniques that are simpler, more scalable and compatible with large-area manufacturing are required. This thesis explores the technological potential of two recently developed patterning techniques namely interlayer lithography (IL) and adhesion-lithography (a-Lith) for application in the field of large-area nano/electronics. The IL method relies on the use of a pre-patterned metal electrode that acts as the mask during back illumination of a photoresist layer followed by a conventional lift-off process step. On the other hand in the a-Lith approach, the surface energy of a patterned metal electrode is modified through the use of surface energy modifiers such as organic self-assembling monolayer (SAM). Following, a second metal is evaporated on the entire substrate. However, because of the present of the SAM, regions of metal-2 overlapping with metal-1 can easily be peeled off with the aid of an adhesive layer (e.g. sticky tape) leaving behind the two metal electrodes in close proximity to each other. Analysis of the resulting structures reveals that inter-electrode distances <20 nm can easily be achieved. The method was then used to develop innovative process protocols for the fabrication of functional self-aligned gate (SAG) transistor architectures. Best performing devices exhibited charge carrier mobility in the range of 0.5-1 cm2/Vs, high current on-off ratio (~104), negligible operating hysteresis and excellent switching speed. Using the same a-Lith process protocol, low-voltage organic ferroelectric tunnel junction memory devices were also developed by combining the metal-1/metal-2 nanogap electrodes with a ferroelectric copolymer deposited in-between them. Controllable ferroelectric tunnelling was observed enabling the devices’ conductivity to be programmed using low biases and hence been used as a non-volatile memory cell. The alternative and highly scalable patterning methods described in this thesis may one day play a significant role on how largearea electronics of the future would be manufactured.Open Acces

Investigation of high-K dielectric films incorporated with Lanthanum and their application in flash memory devices

Ph.DDOCTOR OF PHILOSOPH

Etude d'architectures et d'empilements innovants de mémoires Split-Gate (grille séparée) à couche de piégeage discret

Du fait de l'augmentation de la demande de produits pour les applications grand public, industrielles et automobiles, des mémoires embarquées fiables et à faible coût de fabrication sont de plus en plus demandées. Dans ce contexte, les mémoires split-gate à piégeage discret sont proposées pour des microcontrôleurs. Elles combinent l'avantage d'une couche de stockage discrète et de la con guration split-gate. Durant ce travail de recherche, des mémoires split-gate à couche de piégeage discret ayant des longueurs de grille de 20nm sont présentées pour la première fois. Celles-ci on été réalisées avec des nanocristaux de silicium (Si-nc), du nitrure de silicium (SiN) ou un hybride Si-nc/SiN avec diélectrique de control de type SiO2 ou AlO et sont comparées en termes de performances lors des procédures d'eff acement et de rétention. Ensuite, la miniaturisation des mémoires split-gate à piégeage de charge est étudié, en particulier au travers de l'impact de la réduction de la longueur de grille sur la fenêtre de mémorisation, la rétention et la consommation. Le rôle des défauts dans le diélectrique de contrôle (alumine) utilisé dans les mémoires de type TANOS a été étudié. Des travaux ont été menés pour déterminer l'origine des pièges dans ce matériau, par le biais de la simulation atomistique ainsi que d'analyses physico-chimiques précises. Nous avons montré que la concentration de pièges dans AlO pouvait être réduite par ajustement des conditions de procédé de fabrication, débouchant ainsi sur l'amélioration de la rétention dans les mémoires à piégeage de charge. Ce résultat est convenable pour les applications de type embarquéDue to the increasing demand for consumer, industrial and automotive products, highly reliable, and low integration cost embedded memories are more and more required. In this context, split-gate charge trap memories were proposed for microcontroller products, combining the advantage of a discrete storage layer and of the split-gate con guration. In this thesis, split-gate charge trap memories with electrical gate length down to 20nm are presented for the 1st time. Silicon nanocristals (Si-nc), or silicon nitride (SiN) and hybrid Si-nc/SiN based split-gate memories, with SiO2 or AlO control dielectrics, are compared in terms of program erase and retention. Then, the scalability of split-gate charge trap memories is studied, investigating the impact of gate length reduction on the memory window, retention and consumption. We thus studied the role of defects on alumina control dielectric employed in TANOS-like memory. We used atomistic simulation, consolidated by a detailed alumina physico-chemical material analysis, to investigate the origin of traps in alumina. We showed that the trap concentration in AlO can be decreased by adjusting the process conditions leading to improved retention behaviour in charge trap memory, suitable for embedded applications.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Transient Analysis of Warm Electron Injection Programming of Double Gate SONOS Memories by means of Full Band Monte Carlo Simulation

In this paper we investigate "Warm Electron Injection" as a mechanism for NOR programming of double-gate SONOS memories through 2D full band Monte Carlo simulations. Warm electron injection is characterized by an applied VDS smaller than 3.15 V, so that electrons cannot easily accumulate a kinetic energy larger than the height of the Si/SiO2 barrier. We perform a time-dependent simulation of the program operation where the local gate current density is computed with a continuum-based method and is adiabatically separated from the 2D full Monte Carlo simulation used for obtaining the electron distribution in the phase space. In this way we are able to compute the time evolution of the charge stored in the nitride and of the threshold voltages corresponding to forward and reverse bias. We show that warm electron injection is a viable option for NOR programming in order to reduce power supply, preserve reliability and CMOS logic level compatibility. In addition, it provides a well localized charge, offering interesting perspectives for multi-level and dual bit operation, even in devices with negligible short channel effects