CMOS design of chaotic oscillators using state variables: a monolithic Chua's circuit

This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS technology. Starting from a review of available CMOS circuit primitives and their respective merits and drawbacks, the paper proposes a synthesis approach for PWL dynamic systems, based on state-variable methods, and identifies the associated analog operators. The GmC approach, combining quasi-linear VCCS's, PWL VCCS's, and capacitors is then explored regarding the implementation of these operators. CMOS basic building blocks for the realization of the quasi-linear VCCS's and PWL VCCS's are presented and applied to design a Chua's circuit IC. The influence of GmC parasitics on the performance of dynamic PWL systems is illustrated through this example. Measured chaotic attractors from a Chua's circuit prototype are given. The prototype has been fabricated in a 2.4- mu m double-poly n-well CMOS technology, and occupies 0.35 mm/sup 2/, with a power consumption of 1.6 mW for a +or-2.5-V symmetric supply. Measurements show bifurcation toward a double-scroll Chua's attractor by changing a bias current

A 0.18μm CMOS 9mW current-mode FLF linear phase filter with gain boost

“This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”The design and implementation of a CMOS continuous-time follow-the-leader-feedback (FLF) filter is described. The filter is implemented using a fully-differential linear, low voltage and low power consumption operational transconductance amplifier (OTA) based on a source degeneration topology. PSpice simulations using a standard TSMC 0.18 mum CMOS process with 2 V power supply have shown that the cut-off frequency of the filter ranges from 55 MHz to 160 MHz and dynamic range is about 45 dB. The group delay is less than 5% over the whole tuning range; the power consumption is only 9 mW

Low-Voltage High-Linearity Wideband Current Differencing Transconductance Amplifier and Its Application on Current-Mode Active Filter

A low-voltage high-linearity wideband current differencing transconductance amplifier (CDTA) is presented in this paper. The CDTA consists of a current differencing circuit and a cross-coupling transconductance circuit. The PSPICE simulations of the proposed CDTA show a good performance: -3dB frequency bandwith is about 900 MHz, low power consumption is 2.48 mW, input current linear range is ±100 µA and low current-input resistance is less than 20 Ω, high current-output resistance is more than 3 MΩ. PSpice simulations for a current-mode universal filter and a proposed high-order filter are also conducted, and the results verify the validity of the proposed CDTA

A 0.18μm CMOS 300MHz Current-Mode LF Seventh-order Linear Phase Filter for Hard Disk Read Channels

“This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”A 300MHz CMOS seventh-order linear phase gm-C filter based on a current-mode multiple loop feedback (MLF) leap-frog (LF) structure is realized. The filter is implemented using a fully-differential linear operational transconductance amplifier (OTA) based on a source degeneration topology. PSpice simulations using a standard TSMC 0.18μm CMOS process with 2.5V power supply have shown that the cut-off frequency of the filter can be tuned from 260MHz to 320MHz and dynamic range is about 66dB. Group delay ripple is approximately 4.5% over the whole tuning range and maximum power consumption is 210mW

0.5V 3rd-order Tunable gm-C Filter

This paper proposes a 3rd-order gm-C filter that operates with the extremely low voltage supply of 0.5V. The employed transconductor is capable for operating in an extremely low voltage power supply environment. A benefit offered by the employed transconductor is that the filter’s cut-off frequency can be tuned, through a dc control current, for relatively large ranges. The filter structure was designed using normal threshold transistors of a triple-well 0.13μm CMOS process and is operated under a 0.5V supply voltage; its behavior has been evaluated through simulation results by utilizing the Analog Design Environment of the Cadence software

A wideband linear tunable CDTA and its application in field programmable analogue array

This document is the Accepted Manuscript version of the following article: Hu, Z., Wang, C., Sun, J. et al. ‘A wideband linear tunable CDTA and its application in field programmable analogue array’, Analog Integrated Circuits and Signal Processing, Vol. 88 (3): 465-483, September 2016. Under embargo. Embargo end date: 6 June 2017. The final publication is available at Springer via https://link.springer.com/article/10.1007%2Fs10470-016-0772-7 © Springer Science+Business Media New York 2016In this paper, a NMOS-based wideband low power and linear tunable transconductance current differencing transconductance amplifier (CDTA) is presented. Based on the NMOS CDTA, a novel simple and easily reconfigurable configurable analogue block (CAB) is designed. Moreover, using the novel CAB, a simple and versatile butterfly-shaped FPAA structure is introduced. The FPAA consists of six identical CABs, and it could realize six order current-mode low pass filter, second order current-mode universal filter, current-mode quadrature oscillator, current-mode multi-phase oscillator and current-mode multiplier for analog signal processing. The Cadence IC Design Tools 5.1.41 post-layout simulation and measurement results are included to confirm the theory.Peer reviewedFinal Accepted Versio

A CMOS 100 MHz continuous-time seventh order 0.05° equiripple linear phase leapfrog multiple loop feedback Gm-C filter

“This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”A novel 100 MHz CMOS Gm-C seventh-order 0.05° equiripple linear phase low-pass multiple loop feedback (MLF) filter based on leapfrog (LF) topology is presented. The filter is implemented using a fully-differential linear, high performance operational transconductance amplifier (OTA) based on cross-coupled pairs. PSpice simulations in a standard TSMC 0.25 μm CMOS process and with a single 5 V power supply have shown that the cut-off frequency of the filter without and with gain boost ranges from 8-32 MHz and 15-100 MHz, respectively. With gain boost, total harmonic distortion (THD) for a differential input voltage Vid of 315 mVpp at 1 MHz is less than -40 dB, dynamic range at 1% THD is over 55 dB, output noise with bandwidth 500 MHz is only 300 μVRMS, and power consumption is 322 mW

Low-Voltage Ultra-Low-Power Current Conveyor Based on Quasi-Floating Gate Transistors

The field of low-voltage low-power CMOS technology has grown rapidly in recent years; it is an essential prerequisite particularly for portable electronic equipment and implantable medical devices due to its influence on battery lifetime. Recently, significant improvements in implementing circuits working in the low-voltage low-power area have been achieved, but circuit designers face severe challenges when trying to improve or even maintain the circuit performance with reduced supply voltage. In this paper, a low-voltage ultra-low-power current conveyor second generation CCII based on quasi-floating gate transistors is presented. The proposed circuit operates at a very low supply voltage of only ±0.4 V with rail-to-rail voltage swing capability and a total quiescent power consumption of mere 9.5 µW. Further, the proposed circuit is not only able to process the AC signal as it's usual at quasi-floating gate transistors but also the DC which extends the applicability of the proposed circuit. In conclusion, an application example of the current-mode quadrature oscillator is presented. PSpice simulation results using the 0.18 µm TSMC CMOS technology are included to confirm the attractive properties of the proposed circuit

Realization of Resistorless Lossless Positive and Negative Grounded Inductor Simulators Using Single ZC-CCCITA

This paper is in continuation with the very recent work of Prasad et al. [14], wherein new realizations of grounded and floating positive inductor simulator using current differencing transconductance amplifier (CDTA) are reported. The focus of the paper is to provide alternate realizations of lossless, both positive and negative inductor simulators (PIS and NIS) in grounded form using z-copy current-controlled current inverting transconductance amplifier (ZC-CCCITA), which can be considered as a derivative of CDTA, wherein the current differencing unit (CDU) is reduced to a current-controlled current inverting unit. We demonstrate that only a single ZC-CCCITA and one grounded capacitor are sufficient to realize grounded lossless PIS or NIS. The proposed circuits are resistorless whose parameters can be controlled through the bias currents. The workability of the proposed PIS is validated by SPICE simulations on three RLC prototypes

Unconventional Circuit Elements for Ladder Filter Design

Kmitočtové filtry jsou lineární elektrické obvody, které jsou využívány v různých oblastech elektroniky. Současně tvoří základní stavební bloky pro analogové zpracování signálů. V poslední dekádě bylo zavedeno množství aktivních stavebních bloků pro analogové zpracování signálů. Stále však existuje potřeba vývoje nových aktivních součástek, které by poskytovaly nové možnosti a lepší parametry. V práci jsou diskutovány různé aspekty obvodů pracujících v napěťovém, proudovém a smíšném módu. Práce reaguje na dnešní potřebu nízkovýkonových a nízkonapěťových aplikací pro přenosné přístroje a mobilní komunikační systémy a na problémy jejich návrhu. Potřeba těchto výkonných nízkonapěťových zařízení je výzvou návrhářů k hledání nových obvodových topologií a nových nízkonapěťových technik. V práci je popsána řada aktivních prvků, jako například operační transkonduktanční zesilovač (OTA), proudový konvejor II. generace (CCII) a CDTA (Current Differencing Transconductance Amplifier). Dále jsou navrženy nové prvky, jako jsou VDTA (Voltage Differencing Transconductance Amplifier) a VDVTA (Voltage Differencing Voltage Transconductance Amplifier). Všechny tyto prvky byly rovněž implementovány pomocí "bulk-driven" techniky CMOS s cílem realizace nízkonapěťových aplikací. Tato práce je rovněž zaměřena na náhrady klasických induktorů syntetickými induktory v pasivních LC příčkových filtrech. Tyto náhrady pak mohou vést k syntéze aktivních filtrů se zajímavými vlastnostmi.Frequency filters are linear electric circuits that are used in wide area of electronics. They are also the basic building blocks in analogue signal processing. In the last decade, a huge number of active building blocks for analogue signal processing was introduced. However, there is still the need to develop new active elements that offer new possibilities and better parameters. The current-, voltage-, or mixed-mode analog circuits and their various aspects are discussed in the thesis. This work reflects the trend of low-power (LP) low-voltage (LV) circuits for portable electronic and mobile communication systems and the problems of their design. The need for high-performance LV circuits encourages the analog designers to look for new circuit architectures and new LV techniques. This thesis presents various active elements such as Operational Transconductance Amplifier (OTA), Current Conveyor of Second Generation (CCII), and Current Differencing Transconductance Amplifier (CDTA), and introduces novel ones, such as Voltage Differencing Transconductance Amplifier (VDTA) and Voltage Differencing Voltage Transconductance Amplifier (VDVTA). All the above active elements were also designed in CMOS bulk-driven technology for LP LV applications. This thesis is also focused on replacement of conventional inductors by synthetic ones in passive LC ladder filters. These replacements can lead to the synthesis of active filters with interesting parameters.