Energy Efficient RF Transmitter Design using Enhanced Breakdown Voltage SOI-CMOS Compatible MESFETs

abstract: The high cut-off frequency of deep sub-micron CMOS technologies has enabled the integration of radio frequency (RF) transceivers with digital circuits. However, the challenging point is the integration of RF power amplifiers, mainly due to the low breakdown voltage of CMOS transistors. Silicon-on-insulator (SOI) metal semiconductor field effect transistors (MESFETs) have been introduced to remedy the limited headroom concern in CMOS technologies. The MESFETs presented in this thesis have been fabricated on different SOI-CMOS processes without making any change to the standard fabrication steps and offer 2-30 times higher breakdown voltage than the MOSFETs on the same process. This thesis explains the design steps of high efficiency and wideband RF transmitters using the proposed SOI-CMOS compatible MESFETs. This task involves DC and RF characterization of MESFET devices, along with providing a compact Spice model for simulation purposes. This thesis presents the design of several SOI-MESFET RF power amplifiers operating at 433, 900 and 1800 MHz with ~40% bandwidth. Measurement results show a peak power added efficiency (PAE) of 55% and a peak output power of 22.5 dBm. The RF-PAs were designed to operate in Class-AB mode to minimize the linearity degradation. Class-AB power amplifiers lead to poor power added efficiency, especially when fed with signals with high peak to average power ratio (PAPR) such as wideband code division multiple access (W-CDMA). Polar transmitters have been introduced to improve the efficiency of RF-PAs at backed-off powers. A MESFET based envelope tracking (ET) polar transmitter was designed and measured. A low drop-out voltage regulator (LDO) was used as the supply modulator of this polar transmitter. MESFETs are depletion mode devices; therefore, they can be configured in a source follower configuration to have better stability and higher bandwidth that MOSFET based LDOs. Measurement results show 350 MHz bandwidth while driving a 10 pF capacitive load. A novel polar transmitter is introduced in this thesis to alleviate some of the limitations associated with polar transmitters. The proposed architecture uses the backgate terminal of a partially depleted transistor on SOI process, which relaxes the bandwidth and efficiency requirements of the envelope amplifier in a polar transmitter. The measurement results of the proposed transmitter demonstrate more than three times PAE improvement at 6-dB backed-off output power, compared to the traditional RF transmitters.Dissertation/ThesisPh.D. Electrical Engineering 201

CMOS로 제어되는 GaN HEMT Supply Modulator를 이용한 고효율 Average Power Tracking 전력 증폭기

학위논문 (석사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2013. 8. 권영우.본 논문에서는 Cree사의 CGH60시리즈 GaN HEMT bare die칩으로 제작된 PA를 이용한 Average Power Tracking (APT) 시스템이 구현되었다. 전원 변조기의 제어 회로로써 IBM 0.18um SOI 2.5V RF 공정이 사용되었다. 전원 변조기로는 Class E2 DC-DC컨버터가 사용되었다. Class-E 인버터와 Class-E정류기에 필요한 스위치로는 GaN HEMT가 사용되었다. 두 스위치 모두 CMOS회로에서 펄스 폭 변조 (PWM)방식으로 만들어진 펄스로 제어되었다. 공급 전압 28V와 1MHz PWM신호를 사용한 결과 듀티가 0.5일 때 최대 효율 85%와 31V의 출력 전압을 얻을 수 있었다. GaN HEMT를 이용하여 5.8GHz 고효율 2-단 Class-E 전력 증폭기도 제작되었다. 수치 해석적으로 초기 디자인이 진행되었으며, lumped 소자들은 모두 마이크로스트립으로 대체되었다. 측정 결과 39dBm에서 63.9%의 효율을 얻을 수 있었으며 그때의 전력 이득은 15.8dB였다. Power-단의 드레인 효율은 76%였다. 백오프 구간에서의 효율을 올리기 위해 APT 시스템이 적용되었다. 시스템의 Power-단 드레인 효율은 6dB 백오프 지점에서 1%증가하였으며 9dB 백오프 지점에서 5.7% 증가하였다. 전원 변조기의 최대 출력 전압은 32V로 부스팅 되기 때문에 최대 출력 전력은 37.9dBm에서 38.7dBm으로 증가하였다. 전원 변조기를 제어하기 위해 펄스 폭과 주파수 변조 (PWFM)방식이 PWM대신 제안되었다. 제안된 전원 변조기는 12V출력전압일 때 11%의 효율 증가를 보여주었으며 따라서 넓은 출력 전압 영역에서 70%이상의 효율을 보여주었다. 같은 PA에 APT를 적용한 결과 39.6dBm에서 최대 PAE 49.5%를 얻을 수 있었다. 6dB와 9dB백오프 지점에서의 효율은 각각 4%와 3.5%씩 증가하였다.In this thesis, an Average Power Tracking (APT) system of a Power Amplifier (PA) using Cree Inc. CGH60 series GaN HEMT bare die is presented. IBM 0.18um SOI 2.5V RF technology is used to fabricate control circuits in supply modulator. A Class E2 DC-DC Converter is adopted as the supply modulator. Both Class-E inverter switch and Class-E rectifier switch uses GaN HEMT as a switch. Both switches are controlled by Pulse Width Modulation (PWM) generated by CMOS control circuit. The peak efficiency is 85% at 31V of output voltage with 0.5 duty cycle of 1MHz PWM when 28V is supplied. Highly efficient 5.8GHz 2-Stage Class-E Power Amplifier is realized with GaN HEMT device. Numerical analysis has performed for initial design of PA then the ideal lumped elements are replaced with microstrip lines. The measurement results show the maximum PAE of 63.9% at 39.0dBm of output power with 15.8dB gain. The maximum power-stage drain efficiency is 76% Average Power Tracking is applied in order to increase power-stage drain efficiency at back-off power. The system shows 1% of drain efficiency increment at 6-dB back-off and 5.7% increment at 9-dB back-off power. Since the supply modulator boosts up to 32-V, the maximum output power is increased to 38.7dBm from 37.9dBm. Pulse Width and Frequency Modulation (PWFM) control method is introduced in place PWM control in supply modulator. The new supply modulator shows 11% of efficiency increment at 12V resulting in higher than 70% of efficiency over wide output voltage range. When Average Power Tracking is applied with the same PA, the peak PAE of 49.5% at 39.6dBm with gain of 15.6dB is resulted. At 6 dB and 9 dB back-off power, 4% and 3.5% of PAE is increased.Abstract Table of Contents List of Figures List of Tables 1. Introduction 2. Supply Modulator 2.1. Introduction 2.2. Class E2 DC-DC Converter 2.3. PWM Controlled Supply Modulator 2.3.1. Pulse Width Modulation (Inverter Switch Control) 2.3.2. Rectifier Switch Control 2.4. CMOS Control Circuit 2.4.1. Operational Amplifier 2.4.2. Comparator 2.4.3. Hysteresis Comparator 2.4.4. Voltage Regulator 2.4.5. Gate Driver 2.4.6. Layout 2.5. Measurement: Hybrid Modulator with CMOS and GaN HEMT 2.5.1. CMOS Control Circuit Results 2.5.2. Hybrid Modulator Results 2.6. Future Work 2.7. Conclusion 3. Power Amplifier 3.1. Introduction 3.2. Class E Power Amplifier 3.3. Extraction of Parasitic Elements 3.4. Two-Stage Class-E Power Amplifier 3.4. Measurement: Class E Two Stage Power Amplifier 3.5. Conclusion 4. Average Power Tracking System I 4.1. Introduction 4.2. Expected Overall PAE Calculation 4.3. Synchronization of Supply Modulator with Power Amplifier 4.3. Measurement: Average Power Tracking Power Amplifier I 4.4. Conclusion 5. Average Power Tracking System II 5.1. Introduction 5.2. Concept of PWFM 5.3. Measurement: PWFM Controlled Supply Modulator 5.4. Highly Efficient 5.8GHz Power Amplifier 5.5. Measurement: Average Power Tracking Power Amplifier II 5.6. Conclusion 6. Conclusion Reference Appendix Notes 초록 AcknowledgementMaste

Two-Phase DC-DC Buck Converter for Power Amplifier Modulation

This thesis presents the theory, design, layout and a proposal for measurement set up of a synchronous DC-DC buck converter. This converter will be used as the supply modulator of power amplifier of mobile phones. The design is done using 45nm CMOS technology. Pmos and nmos switches are synchronously turns on and off for DC voltage conversion. Second order LC type filter is used to filter out the ac component from output. Two phase interleaving is done to reduce the output ripple voltage. Pulse Width Modulation (PWM) method is used for generating the control signal. Several techniques like dead time control mechanism, reduced gate drive voltage for switches are applied for improving the efficiency of the converter. The operating voltage range of the converter is 3.3-4.2V and it can produce 0.5-3V output voltage with 2W of maximum output power. It has maximum load current of 700mA. The switching frequency of the converter can be varied from 10MHz to 100MHz. The ripple voltage is less than 10mV for 50MHz switching frequency. The converter shows good results in terms of power density and simulated efficiency which are 1.65W/mm2 and 88.5%

Amplificador de potência para sistemas 5G

In recent years, 5G systems have been in the spotlight and the discussion of how its requirements will change people’s lives is becoming increasingly more relevant. The fact that one of these requirements is to provide users with hundreds of MHz of available bandwidth, coupled with a scarce and crowded spectrum below 3GHz, has led to an increase in the operating frequency. Following this idea, this dissertation has the objective to design, implement and test a power amplifier for 5G systems, specifically for frequencies in the X band (8-12GHz). In this frequency band, the behaviour of RF components (capacitors) and other structures (via hole, substrate and connectors) have to be carefully analysed in order to better understand how these elements can affect the overall performance of the circuits. For this purpose several test circuits were designed, implemented and then, the simulated and measured results were compared. This initial step on the practical work allowed to make some updates on the simulation process and to draw other useful conclusions. After that, the design of a power amplifier for the X band was conceived. In order to reach the final objective, several intermediate prototypes were designed to make possible the identification and correction of potential error sources, for example in the matching networks and in the transistor model. In the end, a power amplifier for the frequency band of 9 to 9.6GHz, which means, 600MHz of bandwidth, was designed and implemented. The maximum drain efficiency achieved was 41-55% with a gain between 6-12dB. These results have proved to be competitive with the actual state-of-the-art. All design and simulation were performed using the Advanced Design System 2019 and Momentum software from Keysight Technologies.Nos últimos anos, os sitemas 5G têm estado em destaque e a forma como os seus requisitos irão mudar a vida da sociedade está a tornar-se ainda mais relevante. O facto de um desses requisitos ser providenciar os utilizadores com centenas de MHz de largura de banda, juntamente com um espetro escasso e lotado abaixo dos 3GHz, levou a um aumento da frequência de operação. Seguindo esta ideia, esta dissertação tem como objetivo projetar, implementar e testar um amplificador de potência para sistemas 5G, em particular para a banda X (8-12GHz). Nesta banda de frequências, o comportamento dos componentes de RF (condensadores) e outras estruturas (vias, substrato e conetores) têm de ser cuidadosamente analisados de modo a entender como é que estes elementos podem afetar o desempenho geral dos circuitos. Com esse propósito, vários circuitos de teste foram projetados, implementados, e de seguida, os resultados simulados e medidos foram comparados. Este passo inicial no trabalho prático permitiu fazer algumas atualizações no processo de simulação e tirar outras conclusões úteis. Posteriormente, um amplificador de potência para a banda X foi concebido. Para atingir o objetivo final, foram projetados vários protótipos intermédios de modo a tornar possível a identificação e correção de potenciais fontes de erro, como por exemplo nas malhas de adaptação e no modelo do transístor. No final foi possível projetar e implementar um amplificador de potência para a banda de frequências de 9 a 9.6GHz, ou seja, com 600MHz de largura de banda. A eficiência de dreno máxima alcançada foi de 41-55% com um ganho entre 6-12dB. Estes resultados demonstraram-se competitivos com o estado-da-arte atual. Todo o projeto e simulação foram realizados usando o software Advanced Design System 2019 e Momentum da Keysight Technologies.Mestrado em Engenharia Eletrónica e Telecomunicaçõe

Design of a Power Amplifier and Envelope Amplifier for a Multi-band Multi-standard Envelope Tracking System

This thesis presents the design of a Power Amplifier (PA) and envelope amplifier for an Envelope Tracking (ET) system that is aimed at meeting emerging radio standards in terms of power efficiency and linearity. The class J mode of operation, as well as the efficiency and power contours from load pull was exploited to develop an adequate procedure for the design of a broadband and high efficiency radio frequency PA. An in-depth study has also been conducted for a hybrid envelope amplifier topology in order to optimize it for power efficiency through proper setting of its switching stage supply. Two separate proof of concept prototypes of the PA and envelop amplifier were designed, fabricated and tested. The PA designed was able to achieve an average drain efficiency of 73.6%, average output power of 45.89dBm, and an average gain of 18dB between 650MHz and 1.050GHz (48% bandwidth). The envelope amplifier achieved close to 74.6% efficiency for a 5MHz bandwidth LTE signal envelope with 6.4dB peak to average power ratio

Analysis and design of ΣΔ Modulators for Radio Frequency Switchmode Power Amplifiers

Power amplifiers are an integral part of every basestation, macrocell, microcell and mobile phone, enabling data to be sent over the distances needed to reach the receiver’s antenna. While linear operation is needed for transmitting WCDMA and OFDM signals, linear operation of a power amplifier is characterized by low power efficiency, and contributes to unwanted power dissipation in a transmitter. Recently, a switchmode power amplifier operation was considered for reducing power losses in a RF transmitter. A linear and efficient operation of a PA can be achieved when the transmitted RF signal is ΣΔ modu- lated, and subsequently amplified by a nonlinear device. Although in theory this approach offers linearity and efficiency reaching 100%, the use of ΣΔ modulation for transmitting wideband signals causes problems in practical implementation: it requires high sampling rate by the digital hardware, which is needed for shaping large contents of a quantization noise induced by the modulator but also, the binary output from the modulator needs an RF power amplifier operating over very wide frequency band. This thesis addresses the problem of noise shaping in a ΣΔ modulator and nonlinear distortion caused by broadband operation in switchmode power amplifier driven by a ΣΔ modulated waveform. The problem of sampling rate increase in a ΣΔ modulator is solved by optimizing structure of the modulator, and subsequent processing of an input signal’s samples in parallel. Independent from the above, a novel technique for reducing quan- tization noise in a bandpass ΣΔ modulator using single bit quantizer is presented. The technique combines error pulse shaping and 3-level quantization for improving signal to noise ratio in a 2-level output. The improvement is achieved without the increase of a digital hardware’s sampling rate, which is advantageous also from the perspective of power consumption. The new method is explored in the course of analysis, and verified by simulated and experimental results. The process of RF signal conversion from the Cartesian to polar form is analyzed, and a signal modulator for a polar transmitter with a ΣΔ-digitized envelope signal is designed and implemented. The new modulator takes an advantage of bandpass digital to analog conversion for simplifying the analog part of the modulator. A deformation of the pulsed RF signal in the experimental modulator is demonstrated to have an effect primarily on amplitude of the RF signal, which is correctable with simple predistortion

Advanced High Efficiency Architectures for Next Generation Wireless Communications

L'abstract è presente nell'allegato / the abstract is in the attachmen

Concurrent Dual-band Doherty Power Amplifiers for Carrier Aggregation

Carrier aggregation is the main feature of the Long Term Evolution advanced (LTE-A) standard to increase the spectral efficiency and communication bandwidth. It calls for wireless transmitters to be multi-band and multi-standard to meet the demands of various deployment scenarios. In addition, these transmit radios must efficiently amplify signals characterized with a high peak-to-average power ratio (PAPR), which is caused by advanced modulation schemes. These two factors highlight the need for the multi-band Doherty power amplifier (DPA), which allows the transmitter remain in high efficiency at back-off power levels and maintain that high efficiency over multiple frequency bands. In this work, a novel output combining network is presented for the dual-band DPA design with extended fractional bandwidth for carrier aggregated signals. The proposed output combiner employs a modified Pi-shape network, which enables the absorption of output capacitances from both the main and peaking devices and eliminates the need for phase offset lines which are major sources of bandwidth limitation in the existing multiband DPAs. In addition to performing the impedance inversion, the proposed combiner incorporates the biasing feeds and presents small low-frequency impedances to both the main and peaking transistors. The inclusion of the bias feeds and small low low-frequency impedance feature improves the linearizability of the DPA when stimulated with concurrent dual-band modulated signals. Lastly, by using the gain contour at the back-off power level, the non-linear AM-AM response caused by the varying input capacitance of the main transistor is mitigated. The proposed dual-band output power combiner and the back-off gain contour technique were applied to design of a dual-band two-way Doherty PA using the commercialized 25W Gallium Nitride (GaN) transistor. Measurement of the two-way DPA shows a gain of 7.5- 9.5 dB at 2.05 - 2.3 GHz and 9 - 11 dB at 3.2 - 3.62 GHz. The efficiency at 6 dB back off is greater than 49% and 47% across the two frequency bands. The linearizability of the dual-band DPA is validated using various carrier aggregated signals. The PA exhibits linear behaviour when driven by up to 80 MHz intra-band carrier aggregated signal and 20 MHz concurrent dual-band signal after DPD. Additionally, carrier aggregated signals usually lead to a PAPR value between 8-10 dB. The efficiency of classic two-way DPA deteriorates when dealing with such signals. To cope with the efficiency deterioration, a three-way DPA was designed. Simulations of the three-way DPA show that the gain is greater than 9 dB within the two frequency bands, 2.05 - 2.32 GHz and 3.35 - 3.65 GHz. The efficiency at 10-dB back-off is greater than 40% in the two frequency bands

Advances in Integrated Circuit Design and Implementation for New Generation of Wireless Transceivers

User’s everyday outgrowing demand for high-data and high performance mobile devices pushes industry and researchers into more sophisticated systems to fulfill those expectations. Besides new modulation techniques and new system designs, significant improvement is required in the transceiver building blocks to handle higher data rates with reasonable power efficiency. In this research the challenges and solution to improve the performance of wireless communication transceivers is addressed. The building block that determines the efficiency and battery life of the entire mobile handset is the power amplifier. Modulations with large peak to average power ratio severely degrade efficiency in the conventional fixed-biased power amplifiers (PAs). To address this challenge, a novel PA is proposed with an adaptive load for the PA to improve efficiency. A nonlinearity cancellation technique is also proposed to improve linearity of the PA to satisfy the EVM and ACLR specifications. Ultra wide-band (UWB) systems are attractive due to their ability for high data rate, and low power consumption. In spite of the limitation assigned by the FCC, the coexistence of UWB and NB systems are still an unsolved challenge. One of the systems that is majorly affected by the UWB signal, is the 802.11a system (5 GHz Wi-Fi). A new analog solution is proposed to minimize the interference level caused by the impulse Radio UWB transmitter to nearby narrowband receivers. An efficient 400 Mpulse/s IR-UWB transmitter is implemented that generates an analog UWB pulse with in-band notch that covers the majority of the UWB spectrum. The challenge in receiver (RX) design is the over increasing out of blockers in applications such as cognitive and software defined radios, which are required to tolerate stronger out-of-band (OB) blockers. A novel RX is proposed with a shunt N-path high-Q filter at the LNA input to attenuate OB-blockers. To further improve the linearity, a novel baseband blocker filtering techniques is proposed. A new TIA has been designed to maintain the good linearity performance for blockers at large frequency offsets. As a result, a +22 dBm IIP3 with 3.5 dB NF is achieved. Another challenge in the RX design is the tough NF and linearity requirements for high performance systems such as carrier aggregation. To improve the NF, an extra gain stage is added after the LNA. An N-path high-Q band-pass filter is employed at the LNA output together with baseband blocker filtering technique to attenuate out-of-band blockers and improve the linearity. A noise-cancellation technique based on the frequency translation has been employed to improve the NF. As a result, a 1.8dB NF with +5 dBm IIP3 is achieved. In addition, a new approach has been proposed to reject out of band blockers in carrier aggregation scenarios. The proposed solution also provides carrier to carrier isolation compared to typical solution for carrier aggregation

CMOS Integrated Power Amplifiers for RF Reconfigurable and Digital Transmitters

abstract: This dissertation focuses on three different efficiency enhancement methods that are applicable to handset applications. These proposed designs are based on three critical requirements for handset application: 1) Small form factor, 2) CMOS compatibility and 3) high power handling. The three presented methodologies are listed below: 1) A transformer-based power combiner architecture for out-phasing transmitters 2) A current steering DAC-based average power tracking circuit for on-chip power amplifiers (PA) 3) A CMOS-based driver stage for GaN-based switched-mode power amplifiers applicable to fully digital transmitters This thesis highlights the trends in wireless handsets, the motivates the need for fully-integrated CMOS power amplifier solutions and presents the three novel techniques for reconfigurable and digital CMOS-based PAs. Chapter 3, presents the transformer-based power combiner for out-phasing transmitters. The simulation results reveal that this technique is able to shrink the power combiner area, which is one of the largest parts of the transmitter, by about 50% and as a result, enhances the output power density by 3dB. The average power tracking technique (APT) integrated with an on-chip CMOS-based power amplifier is explained in Chapter 4. This system is able to achieve up to 32dBm saturated output power with a linear power gain of 20dB in a 45nm CMOS SOI process. The maximum efficiency improvement is about ∆η=15% compared to the same PA without APT. Measurement results show that the proposed method is able to amplify an enhanced-EDGE modulated input signal with a data rate of 70.83kb/sec and generate more than 27dBm of average output power with EVM<5%. Although small form factor, high battery lifetime, and high volume integration motivate the need for fully digital CMOS transmitters, the output power generated by this type of transmitter is not high enough to satisfy the communication standards. As a result, compound materials such as GaN or GaAs are usually being used in handset applications to increase the output power. Chapter 5 focuses on the analysis and design of two CMOS based driver architectures (cascode and house of cards) for driving a GaN power amplifier. The presented results show that the drivers are able to generate ∆Vout=5V, which is required by the compound transistor, and operate up to 2GHz. Since the CMOS driver is expected to drive an off-chip capacitive load, the interface components, such as bond wires, and decoupling and pad capacitors, play a critical role in the output transient response. Therefore, extensive analysis and simulation results have been done on the interface circuits to investigate their effects on RF transmitter performance. The presented results show that the maximum operating frequency when the driver is connected to a 4pF capacitive load is about 2GHz, which is perfectly matched with the reported values in prior literature.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201