1,551 research outputs found
Flexible and Low-Complexity Encoding and Decoding of Systematic Polar Codes
In this work, we present hardware and software implementations of flexible
polar systematic encoders and decoders. The proposed implementations operate on
polar codes of any length less than a maximum and of any rate. We describe the
low-complexity, highly parallel, and flexible systematic-encoding algorithm
that we use and prove its correctness. Our hardware implementation results show
that the overhead of adding code rate and length flexibility is little, and the
impact on operation latency minor compared to code-specific versions. Finally,
the flexible software encoder and decoder implementations are also shown to be
able to maintain high throughput and low latency.Comment: Submitted to IEEE Transactions on Communications, 201
Scalable Successive-Cancellation Hardware Decoder for Polar Codes
Polar codes, discovered by Ar{\i}kan, are the first error-correcting codes
with an explicit construction to provably achieve channel capacity,
asymptotically. However, their error-correction performance at finite lengths
tends to be lower than existing capacity-approaching schemes. Using the
successive-cancellation algorithm, polar decoders can be designed for very long
codes, with low hardware complexity, leveraging the regular structure of such
codes. We present an architecture and an implementation of a scalable hardware
decoder based on this algorithm. This design is shown to scale to code lengths
of up to N = 2^20 on an Altera Stratix IV FPGA, limited almost exclusively by
the amount of available SRAM
A Multi-Kernel Multi-Code Polar Decoder Architecture
Polar codes have received increasing attention in the past decade, and have
been selected for the next generation of wireless communication standard. Most
research on polar codes has focused on codes constructed from a
polarization matrix, called binary kernel: codes constructed from binary
kernels have code lengths that are bound to powers of . A few recent works
have proposed construction methods based on multiple kernels of different
dimensions, not only binary ones, allowing code lengths different from powers
of . In this work, we design and implement the first multi-kernel successive
cancellation polar code decoder in literature. It can decode any code
constructed with binary and ternary kernels: the architecture, sized for a
maximum code length , is fully flexible in terms of code length, code
rate and kernel sequence. The decoder can achieve frequency of more than
GHz in nm CMOS technology, and a throughput of Mb/s. The area
occupation ranges between mm for and mm for
. Implementation results show an unprecedented degree of
flexibility: with , up to code lengths can be decoded with
the same hardware, along with any kernel sequence and code rate
Partial Sums Generation Architecture for Successive Cancellation Decoding of Polar Codes
Polar codes are a new family of error correction codes for which efficient
hardware architectures have to be defined for the encoder and the decoder.
Polar codes are decoded using the successive cancellation decoding algorithm
that includes partial sums computations. We take advantage of the recursive
structure of polar codes to introduce an efficient partial sums computation
unit that can also implements the encoder. The proposed architecture is
synthesized for several codelengths in 65nm ASIC technology. The area of the
resulting design is reduced up to 26% and the maximum working frequency is
improved by ~25%.Comment: Submitted to IEEE Workshop on Signal Processing Systems (SiPS)(26
April 2012). Accepted (28 June 2013
- …