8,452 research outputs found

    Modem design for a MOBILESAT terminal

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    The implementation is described of a programmable digital signal processor based system, designed for use as a test bed in the development of a digital modem, codec, and channel simulator. Code was written to configure the system as a 5600 bps or 6600 bps QPSK modem. The test bed is currently being used in an experiment to evaluate the performance of digital speech over shadowed channels in the Australian mobile satellite (MOBILESAT) project

    Radio Link Simulator

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    The need for transmission of data over HF and VJUHF radio is increasing. There is a major disadvantage in testing the link in a field trial as propagation condition of the medium (especially HF) can be unpredictable and link condition may never again be the same. A simulator to create the atmospheric conditions, repeatably as required,to test the system behaviour is evident. The various propagation effects can be mathematically modelled, to get the signal affected by thechannel. Models for Gaussian, Rayleigh and Rice distributions and the implementation of the simulator using latest state-of-the-art DSP techniques are discussed

    An AER Spike-Processing Filter Simulator and Automatic VHDL Generator Based on Cellular Automata

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    Spike-based systems are neuro-inspired circuits implementations traditionally used for sensory systems or sensor signal processing. Address-Event- Representation (AER) is a neuromorphic communication protocol for transferring asynchronous events between VLSI spike-based chips. These neuro-inspired implementations allow developing complex, multilayer, multichip neuromorphic systems and have been used to design sensor chips, such as retinas and cochlea, processing chips, e.g. filters, and learning chips. Furthermore, Cellular Automata (CA) is a bio-inspired processing model for problem solving. This approach divides the processing synchronous cells which change their states at the same time in order to get the solution. This paper presents a software simulator able to gather several spike-based elements into the same workspace in order to test a CA architecture based on AER before a hardware implementation. Furthermore this simulator produces VHDL for testing the AER-CA into the FPGA of the USBAER AER-tool.Ministerio de Ciencia e Innovación TEC2009-10639-C04-0

    Tactical Electronics Simulation Test System : Feasibility Assessment Briefing CDRL A003, B002

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    This volume entirely consists of viewgraphs used to present feasibility assessment contained in related volume, Feasibility assessment report CDRL A002

    PROGRAPE-1: A Programmable, Multi-Purpose Computer for Many-Body Simulations

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    We have developed PROGRAPE-1 (PROgrammable GRAPE-1), a programmable multi-purpose computer for many-body simulations. The main difference between PROGRAPE-1 and "traditional" GRAPE systems is that the former uses FPGA (Field Programmable Gate Array) chips as the processing elements, while the latter rely on the hardwired pipeline processor specialized to gravitational interactions. Since the logic implemented in FPGA chips can be reconfigured, we can use PROGRAPE-1 to calculate not only gravitational interactions but also other forms of interactions such as van der Waals force, hydrodynamical interactions in SPH calculation and so on. PROGRAPE-1 comprises two Altera EPF10K100 FPGA chips, each of which contains nominally 100,000 gates. To evaluate the programmability and performance of PROGRAPE-1, we implemented a pipeline for gravitational interaction similar to that of GRAPE-3. One pipeline fitted into a single FPGA chip, which operated at 16 MHz clock. Thus, for gravitational interaction, PROGRAPE-1 provided the speed of 0.96 Gflops-equivalent. PROGRAPE will prove to be useful for wide-range of particle-based simulations in which the calculation cost of interactions other than gravity is high, such as the evaluation of SPH interactions.Comment: 20 pages with 9 figures; submitted to PAS
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