Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

An Energy-Efficient Reconfigurable Mobile Memory Interface for Computing Systems

The critical need for higher power efficiency and bandwidth transceiver design has significantly increased as mobile devices, such as smart phones, laptops, tablets, and ultra-portable personal digital assistants continue to be constructed using heterogeneous intellectual properties such as central processing units (CPUs), graphics processing units (GPUs), digital signal processors, dynamic random-access memories (DRAMs), sensors, and graphics/image processing units and to have enhanced graphic computing and video processing capabilities. However, the current mobile interface technologies which support CPU to memory communication (e.g. baseband-only signaling) have critical limitations, particularly super-linear energy consumption, limited bandwidth, and non-reconfigurable data access. As a consequence, there is a critical need to improve both energy efficiency and bandwidth for future mobile devices.;The primary goal of this study is to design an energy-efficient reconfigurable mobile memory interface for mobile computing systems in order to dramatically enhance the circuit and system bandwidth and power efficiency. The proposed energy efficient mobile memory interface which utilizes an advanced base-band (BB) signaling and a RF-band signaling is capable of simultaneous bi-directional communication and reconfigurable data access. It also increases power efficiency and bandwidth between mobile CPUs and memory subsystems on a single-ended shared transmission line. Moreover, due to multiple data communication on a single-ended shared transmission line, the number of transmission lines between mobile CPU and memories is considerably reduced, resulting in significant technological innovations, (e.g. more compact devices and low cost packaging to mobile communication interface) and establishing the principles and feasibility of technologies for future mobile system applications. The operation and performance of the proposed transceiver are analyzed and its circuit implementation is discussed in details. A chip prototype of the transceiver was implemented in a 65nm CMOS process technology. In the measurement, the transceiver exhibits higher aggregate data throughput and better energy efficiency compared to prior works

Proposed 10-bit 1 Ghz Two-step Analog to Digital Converter for Implementation in Tfsoi

School of Electrical and Computer Engineerin

Oversampled analog-to-digital converter architectures based on pulse frequency modulation

Mención Internacional en el título de doctorThe purpose of this research work is providing new insights in the development of voltage-controlled oscillator based analog-to-digital converters (VCO-based ADCs). Time-encoding based ADCs have become of great interest to the designer community due to the possibility of implementing mostly digital circuits, which are well suited for current deep-submicron CMOS processes. Within this topic, VCO-based ADCs are one of the most promising candidates. VCO-based ADCs have typically been analyzed considering the output phase of the oscillator as a state variable, similar to the state variables considered in __ modulation loops. Although this assumption might take us to functional designs (as verified by literature), it does not take into account neither the oscillation parameters of the VCO nor the deterministic nature of quantization noise. To overcome this issue, we propose an interpretation of these type of systems based on the pulse frequency modulation (PFM) theory. This permits us to analytically calculate the quantization noise, in terms of the working parameters of the system. We also propose a linear model that applies to VCO-based systems. Thanks to it, we can determine the different error processes involved in the digitization of the input data, and the performance limitations which these processes direct to. A generic model for any order open-loop VCO-based ADCs is made based on the PFM theory. However, we will see that only the first-order case and a second order approximation can be implemented in practice. The PFM theory also allows us to propose novel approaches to both single-stage and multistage VCObased architectures. We describe open-loop architectures such as VCO-based architectures with digital precoding, PFM-based architectures that can be used as efficient ADCs or MASH architectures with optimal noise-transfer-function (NTF) zeros. We also make a first approach to the proposal and analysis of closed loop architectures. At the same time, we deal with one of the main limitations of VCOs (especially those built with ring oscillators), which is the non-linear voltage to- frequency relation. In this document, we describe two techniques mitigate this phenomenon. Firstly, we propose to use a pulse width modulator in front of the VCO. This way, there are only two possible oscillation states. Consequently, the oscillator works linearly. To validate the proposed technique, an experimental prototype was implemented in a 40-nm CMOS process. The chip showed noise problems that degraded the expected resolution, but allowed us to verify that the potential performance was close to the expected one. A potential signal-to-noise-distortion ratio (SNDR) equal to 56 dB was achieved in 20 MHz bandwidth, consuming 2.15 mW with an occupied area equal to 0.03 mm2. In comparison to other equivalent systems, the proposed architecture is simpler, while keeping similar power consumption and linearity properties. Secondly, we used a pulse frequency modulator to implement a second ADC. The proposed architecture is intrinsically linear and uses a digital delay line to increase the resolution of the converter. One experimental prototype was implemented in a 40-nm CMOS process using one of these architectures. Proper results were measured from this prototype. These results allowed us to verify that the PFM-based architecture could be used as an efficient ADC. The measured peak SNDR was equal to 53 dB in 20 MHz bandwidth, consuming 3.5 mW with an occupied area equal to 0.08 mm2. The architecture shows a great linearity, and in comparison to related work, it consumes less power and occupies similar area. In general, the theoretical analyses and the architectures proposed in the document are not restricted to any application. Nevertheless, in the case of the experimental chips, the specifications required for these converters were linked to communication applications (e.g. VDSL, VDSL2, or even G.fast), which means medium resolution (9-10 bits), high bandwidth (20 MHz), low power and low area.El propósito del trabajo presentado en este documento es aportar una nueva perspectiva para el diseño de convertidores analógico-digitales basados en osciladores controlados por tensión. Los convertidores analógico-digitales con codificación temporal han llamado la atención durante los últimos años de la comunidad de diseñadores debido a la posibilidad de implementarlos en su gran mayoría con circuitos digitales, los cuales son muy apropiados para los procesos de diseño manométricos. En este ámbito, los convertidores analógico-digitales basados en osciladores controlados por tensión son uno de los candidatos más prometedores. Los convertidores analógico-digitales basados en osciladores controlados por tensión han sido típicamente analizados considerando que la fase del oscilador es una variable de estado similar a las que se observan en los moduladores __. Aunque esta consideración puede llevarnos a diseños funcionales (como se puede apreciar en muchos artículos de la literatura), en ella no se tiene en cuenta ni los parámetros de oscilación ni la naturaleza determinística del ruido de cuantificación. Para solventar esta cuestión, en este documento se propone una interpretación alternativa de este tipo de sistemas haciendo uso de la teoría de la modulación por frecuencia de pulsos. Esto nos permite calcular de forma analítica las ecuaciones que modelan el ruido de cuantificación en función de los parámetros de oscilación. Se propone también un modelo lineal para el análisis de convertidores analógico-digitales basados en osciladores controlados por tensión. Este modelo permite determinar las diferentes fuentes de error que se producen durante el proceso de digitalización de los datos de entrada y las limitaciones que suponen. Un modelo genérico de convertidor de cualquier orden se propone con la ayuda de este modelo. Sin embargo, solo los casos de primer orden y una aproximación al caso de segundo orden se pueden implementar en la práctica. La teoría de la modulación por frecuencia de pulsos también permite nuevas perspectivas para la propuesta y el análisis tanto de arquitecturas de una sola etapa como de arquitecturas de varias etapas construidas con osciladores controlados por tensión. Se proponen y se describen arquitecturas en lazo abierto como son las basadas en osciladores controlador por tensión con moduladores digitales en la etapa de entrada, moduladores por frecuencia de pulsos que se utilizan como convertidores analógico-digitales eficientes o arquitecturas en cascada en las que se optimizan la distribución de los ceros en la función de transferencia del ruido. También se realiza una aproximación a la propuesta y el análisis de arquitecturas en lazo cerrado. Al mismo tiempo, se aborda una de las problemáticas más importantes de los osciladores controlados por tensión (especialmente en aquellos implementados mediante osciladores en anillo): la relación tensión-freculineal que presentan este tipo de circuitos. En el documento, se describen dos técnicas cuyo objetivo es mitigar esta limitación. La primera técnica de corrección se basa en el uso de un modulador por ancho de pulsos antes del oscilador controlado por tensión. De esta forma, solo existen dos estados de oscilación en el oscilador, se trabaja de forma lineal y no se genera distorsión en los datos de salida. La técnica se propone de forma teórica haciendo uso de la teoría desarrollada previamente. Para llevar a cabo la validación de la propuesta teórica se fabricó un prototipo experimental en un proceso CMOS de 40-nm. El chip mostró problemas de ruido que limitaban la resolución, sin embargo, nos permitió velicar que la resolución ideal que se podrá haber obtenido estaba muy cercana a la resolución esperada. Se obtuvo una potencial relación señal-(ruido-distorsión) igual a 56 dB en 20 MHz de ancho de banda, un consumo de 2.15 mW y un área igual a 0.03 mm2. En comparación con sistemas equivalentes, la arquitectura propuesta es más simple al mismo tiempo que se mantiene el consumo así como la linealidad. A continuación, se propone la implementación de un convertidor analógico digital mediante un modulador por frecuencia de pulsos. La arquitectura propuesta es intrínsecamente lineal y hace uso de una línea de retraso digital con el fin de mejorar la resolución del convertidor. Como parte del trabajo experimental, se fabricó otro chip en tecnología CMOS de 40 nm con dicha arquitectura, de la que se obtuvieron resultados notables. Estos resultados permitieron verificar que la arquitectura propuesta, en efecto, podrá emplearse como convertidor analógico-digital eficiente. La arquitectura consigue una relación real señal-(ruido-distorsión) igual a 53 dB en 20 MHz de ancho de banda, un consumo de 3.5 mW y un área igual a 0.08 mm2. Se obtiene una gran linealidad y, en comparación con arquitecturas equivalentes, el consumo es menor mientras que el área ocupada se mantiene similar. En general, las aportaciones propuestas en este documento se pueden aplicar a cualquier tipo de aplicación, independientemente de los requisitos de resolución, ancho de banda, consumo u área. Sin embargo, en el caso de los prototipos fabricados, las especificaciones se relacionan con el ámbito de las comunicaciones (VDSL, VDSL2, o incluso G.fast), en donde se requiere una resolución media (9-10 bits), alto ancho de banda (20 MHz), manteniendo bajo consumo y baja área ocupada.Programa Oficial de Doctorado en Ingeniería Eléctrica, Electrónica y AutomáticaPresidente: Michael Peter Kennedy.- Secretario: Antonio Jesús López Martín.- Vocal: Jörg Hauptman

Efficient Continuous-Time Sigma-Delta Converters for High Frequency Applications

Over the years Continuous-Time (CT) Sigma-Delta (ΣΔ) modulators have received a lot of attention due to their ability to efficiently digitize a variety of signals, and suitability for many different applications. Because of their tolerance to component mismatch, the easy to drive input structure, as well as intrinsic anti-aliasing filtering and noise shaping abilities, CTΣΔ modulators have become one of the most popular data-converter type for high dynamic range and moderate/wide bandwidth. This trend is the result of faster CMOS technologies along with design innovations such as better architectures and faster amplifiers. In other words, CTΣΔ modulators are starting to offer the best of both worlds, with high resolution and high bandwidth. This dissertation focuses on the bandwidth and resolution of CTΣΔ modulators. The goal of this research is to use the noise shaping benefits of CTΣΔ modulators for different wireless applications, while achieving high resolution and/or wide bandwidth. For this purpose, this research focuses on two different application areas that demand speed and resolution. These are a low-noise high-resolution time-to-digital converter (TDC), ideal for digital phase lock loops (PLL), and a very high-speed, wide-bandwidth CTΣΔ modulator for wireless communication. The first part of this dissertation presents a new noise shaping time-to-digital converter, based on a CTΣΔ modulator. This is intended to reduce the in-band phase noise of a high frequency digital phase lock loop (PLL) without reducing its loop bandwidth. To prove the effectiveness of the proposed TDC, 30GHz and a 40GHz fractional-N digital PLL are designed as a signal sources for a 240GHz FMCW radar system. Both prototypes are fabricated in a 65nm CMOS process. The standalone TDC achieves 81dB dynamic range and 13.2 equivalent number of bits (ENOB) with 176fs integrated-rms noise from 1MHz bandwidth. The in-band phase noise of the 30GHz digital fractional-N PLL is measured as -87dBc/Hz at a 100kHz offset which is equivalent to -212.6dBc/Hz2 normalized in-band phase noise. The second part of this dissertation focuses on high-speed (GS/s) CTΣΔ modulators for wireless communication, and introduces a new time-interleaved reference data weighted averaging (TI-RDWA) architecture suitable for GS/s CTΣΔ modulators. This new architecture shapes the digital-to-analog converter (DAC) mismatch effects in a CTΣΔ modulator at GS/s operating speeds. It allows us to use smaller DAC unit sizes to reduce area and power consumption for the same bandwidth. The prototype 5GS/s CTΣΔ modulator with TI-RDWA is fabricated in 40nm CMOS and it achieves 156MHz bandwidth, 70dB dynamic range, 84dB SFDR and a Schreier FoM of 158.3dB.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/138763/1/bdayanik_1.pd

Low Power Continuous-time Bandpass Delta-Sigma Modulators.

Low power techniques for continuous-time bandpass delta-sigma modulators (CTBPDSMs) are introduced. First, a 800MS/s low power 4th-order CTBPDSM with 24MHz bandwidth at 200MHz IF is presented. A novel power-efficient resonator with a single amplifier is used in the loopfilter. A single op-amp resonator makes use of positive feedback to increase the quality factor. Also, a new 4th-order architecture is introduced for system simplicity and low power. Low power consumption and a simple modulator structure are achieved by reducing the number of feedback DACs. This modulator achieves 58dB SNDR, and the total power consumption is 12mW. Second, a 6th-order CTBPDSM with duty cycle controlled DACs is presented. This prototype introduces new architecture for low power consumption and other important features. Duty cycle control enables the use of a single DAC per resonator without degrading the signal transfer function (STF), and helps to lower power consumption, low area, and thermal noise. This ADC provides input signal filtering, and increases the dynamic range by reducing the peaking in the STF. Furthermore, the center frequency is tunable so that the CTBPDSM is more useful in the receiver. The prototype second modulator achieves 69dB SNDR, and consumes 35mW, demonstrating the best FoM of 320fJ/conv.-step for CTBPDSMs using active resonators. The techniques introduced in this research help CTBPDSMs have good power efficiency compared with the other kinds of ADCs, and make the implement of a software-defined radio architecture easier which is appropriate for the future multiple standard radio receivers without a power penalty.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/98001/1/hichae_1.pd

Design and Implementation of an RF Front-End for Software Defined Radios

Software Defined Radios have brought a major reformation in the design standards for radios, in which a large portion of the functionality is implemented through pro­ grammable signal processing devices, giving the radio the ability to change its op­ erating parameters to accommodate new features and capabilities. A software radio approach reduces the content of radio frequency and other analog components of the traditional radios and emphasizes digital signal processing to enhance overall receiver flexibility. Field Programmable Gate Arrays (FPGA) are a suitable technology for the hardware platform as they offer the potential of hardware-like performance coupled with software-like programmability. Software defined radio is a very broad field, encompassing the design of various technologies all the way from the antenna to RF, IF, and baseband digital design. The RF section primarily consists of analog hardware modules. The IF and baseband sections are primarily digital. It is the general process of the radio to convert the incoming signal from RF to IF and then IF to baseband for better signal processing system. In this thesis, some of major building blocks of a Software defined radio are de­ signed and implemented using FPGAs. The design of a Digital front end, which provides the bridge between the baseband and analog RF portions of a wireless receiver, is synthesized. The Digital front end receiver consists of a digital down converter(DDC) which in turn comprises of a direct digital frequency synthesizer (DDFS), a phase accumulator and a low pass filter. The signal processing block of the DDFS is executed using Co-ordinate Rotation Digital Computer (CORDIC) iii Abstract algorithm. Cascaded-Integrator-Comb filters (CIC) are implemented for changing the sample rate of the incoming data. Application of a DDC includes software ra­ dios, multicarrier, multimode digital receivers, micro and pico cell systems,broadband data applications, instrumentation and test equipment and in-building wireless tele­ phony. Also, in this thesis, interfaces for connecting Texas Instruments high speed and high resolution Analog-to-Digital converters (ADC) and Digital-to-Analog converters (DAC) with Xilinx Virtex-5 FPGAs are also implemented and demonstrated

Design of 10 Gb/s burst-mode receivers for high-split extended reach PONs

The continuous stream of new applications for the internet, increases the need for higher access speed in the currently deployed communication networks. Most networks in use today still consist of twisted copper wires, inherited from the telephone network. The disadvantages of reusing the existing telephone network are twofold. Firstly, the bandwidth of twisted copper wires is limited and secondly, a large number of switches and routers are needed throughout the network leading to an excessive power consumption. The hybrid fiber coax network that reuses the television distribution network is not free from these drawbacks. The bandwidth is also limited and power hungry amplifiers are needed to bridge the distance to and from the user. The future of broadband access lies in optical fiber networks. The optical fiber has a virtually unlimited bandwidth and the lower attenuation leads to less switches and amplifiers in the network, reducing the power consumption of the complete infrastructure. This dissertation describes the design of a 10 Gb/s burst-mode receiver for high-split extended reach passive optical networks (PONs). The designed receiver incorporates two very advanced features. Firstly, the burst-mode receiver locks its gain setting within 6 ns avoiding packet loss due to gain switching during data payload reception. Secondly, the burst-mode receiver detects both burst start and burst end, making it the first burst-mode receiver of its kind to operate without any time critical signal requirements from outside the burst-mode receiver. The presented work covers the chip-level architecture study and design of a 10 Gb/s burst-mode transimpedance amplifier and a 10 Gb/s post-amplifier, which are the two most critical components of a burst-mode receiver

Design of sigma-delta modulators for analog-to-digital conversion intensively using passive circuits

This thesis presents the analysis, design implementation and experimental evaluation of passiveactive discrete-time and continuous-time Sigma-Delta (ΣΔ) modulators (ΣΔMs) analog-todigital converters (ADCs). Two prototype circuits were manufactured. The first one, a discrete-time 2nd-order ΣΔM, was designed in a 130 nm CMOS technology. This prototype confirmed the validity of the ultra incomplete settling (UIS) concept used for implementing the passive integrators. This circuit, clocked at 100 MHz and consuming 298 μW, achieves DR/SNR/SNDR of 78.2/73.9/72.8 dB, respectively, for a signal bandwidth of 300 kHz. This results in a Walden FoMW of 139.3 fJ/conv.-step and Schreier FoMS of 168 dB. The final prototype circuit is a highly area and power efficient ΣΔM using a combination of a cascaded topology, a continuous-time RC loop filter and switched-capacitor feedback paths. The modulator requires only two low gain stages that are based on differential pairs. A systematic design methodology based on genetic algorithm, was used, which allowed decreasing the circuit’s sensitivity to the circuit components’ variations. This continuous-time, 2-1 MASH ΣΔM has been designed in a 65 nm CMOS technology and it occupies an area of just 0.027 mm2. Measurement results show that this modulator achieves a peak SNR/SNDR of 76/72.2 dB and DR of 77dB for an input signal bandwidth of 10 MHz, while dissipating 1.57 mW from a 1 V power supply voltage. The ΣΔM achieves a Walden FoMW of 23.6 fJ/level and a Schreier FoMS of 175 dB. The innovations proposed in this circuit result, both, in the reduction of the power consumption and of the chip size. To the best of the author’s knowledge the circuit achieves the lowest Walden FOMW for ΣΔMs operating at signal bandwidth from 5 MHz to 50 MHz reported to date