Monolithic Active Pixel Sensors (MAPS) in a quadruple well technology for nearly 100% fill factor and full CMOS pixels

In this paper we present a novel, quadruple well process developed in a modern 0.18mu CMOS technology called INMAPS. On top of the standard process, we have added a deep P implant that can be used to form a deep P-well and provide screening of N-wells from the P-doped epitaxial layer. This prevents the collection of radiation-induced charge by unrelated N-wells, typically ones where PMOS transistors are integrated. The design of a sensor specifically tailored to a particle physics experiment is presented, where each 50mu pixel has over 150 PMOS and NMOS transistors. The sensor has been fabricated in the INMAPS process and first experimental evidence of the effectiveness of this process on charge collection is presented, showing a significant improvement in efficiency.Comment: 15 pages, 10 figures, submitted to "Sensors

Solid-State Imaging in Standard CMOS Processes

The main aim of this work is to investigate the real CMOS imaging possibilities of standard (not CMOS imaging enhanced) 0.5µm and 0.35µm CMOS processes available for in-house fabrication at the Fraunhofer IMS by performing an extensive study of standard available photodetector structures, mainly based on reverse biased p-n junctions and/or metal-oxide-semiconductor capacitors (MOS-C). Moreover, novel concepts of photodetector pixel structures and readout circuits are proposed, modelled, simulated, fabricated, and characterised, that should achieve an improvement in performance as well as new application developments in the area of CMOS imaging systems. The latter, undergoing as a small amount of changes (extra masks, thermal steps, ion implantations, etc.) as possible within the standard CMOS processes mentioned. In this sense, in Chapter 1 a brief review of the fundamentals of silicon oriented photodetection and electronic devices physics is given, some of the basic postulates of which are directly applied to the case of the 0.5µm standard CMOS process available at the Fraunhofer IMS, whose photodetection possibilities are investigated in detail in Chapter 2. Chapter 3 deals with different pixel configuration possibilities to be fabricated in the 0.5µm process. As a potential solution to overcome some of the problems encountered in Chapter 3, in Chapter 4, the possibilities of using separated photoactive and readout regions in a mixed silicon-on-insulator (SOI) based high-voltage CMOS process developed for automotive industry applications are discussed. Moreover, the same 30V thin-film SOI CMOS process is proposed for direct (not using a scintillator material) X-ray scientific CMOS imaging applications, as it is explained in Chapter 5. In Chapter 6, the photodetection possibilities of the recently developed 0.35µm standard CMOS process available at the Fraunhofer IMS are investigated, as well as different pixel configurations possible to be fabricated in this process. Finally, a discussion is carried out regarding the results obtained throughout the enlisted chapters, and new lines of investigation are attempted to be opened based on some of the results obtained in the present investigation.Das Hauptthema dieser Dissertation ist die Untersuchung vorhandener und neuer Photodetektoren für die CMOS-Bildsensorik, insbesondere in Bezug auf die technologischen und optoelektronischen Eigenschaften sowie das Rauschen. Durch die gründliche Charakterisierung vorhandener und neuer Photodetektoren und deren Ausleseschaltungen, hergestellt in den 0,5µm, 0,35µm und 1,0µm SOI Standard CMOS Prozessen, wurde das vorhandene Wissen vertieft und erweitert. Auf dieser Basis wurden neue Bauelemente für die 2D- und 3D-Bildsensorik entworfen und bereits vorhandene optimiert. Zum besseren Verständnis der Bauelementenstruktur, und um die Anzahl von Fertigungsdurchläufen für neuartige Photodetektorbauelementen zu reduzieren, wurde die Prozess- und Bauelemente-Simulationsumgebung (ISE-Synopsys) TCAD genutzt. Ziel dabei war es, neu entwickelte Bauelemente vor einer Fertigung bezüglich ihrer Schlüsselspezifikationen zu optimieren und qualitativ bewerten zu können. Ferner wurden passende Ausleseschaltungen für die Photodetektorbauelemente entwickelt. Somit konnte ein System aus Photodetektor und Ausleseschaltung optimal auf eine Anwendung abgestimmt werden. Um die Entwurfsicherheit von CMOS Photodetektoren und Ausleseschaltungen zu erhöhen, wurde zur Modellierung von Photodetektorbauelementen mit den Softwarepaketen MAPLE und Fortran eine Entwicklungsumgebung aufgebaut. Auf Basis der so gewonnenen Spezifikationen der Photodetektorstrukturen konnten die gesamten Pixel mit der Schaltungsentwicklungsumgebung CADENCE simuliert werden. Anschließend wurden diese Detektoren und Ausleseschaltungen in den 0,5µm und 0,35µm Standard CMOS Prozessen sowie in dem 1,0µm SOI CMOS Prozess hergestellt und getestet. Um das Signal-Rausch-Verhältnis (SNR) zu verbessern, wurden verschiedenen Pixelkonfigurationen mit voneinander getrennten Photoaktiv- und Auslesegebieten untersucht, wie z.B. in den „Photogate“- oder „Buried-Photodiode“ Aktiv Pixelsensoren. Es wurde allerdings gezeigt, dass die Ladungskopplung, die für die Auslese bei solchen Pixel notwendig ist, bei keiner Kombination der Photodetektoren und der Auslesegebiete im 0,5µm Standard CMOS Prozess funktioniert. Anschließend wurden Untersuchungen von unterschiedlichen Pixelalternativen mit innovativen Ausleseprinzipien durchgeführt. Eines der neu entwickelten Ausleseprinzipien wurde am „Charge-Injection-Photogate-Pixel“ getestet. Durch dieses Ausleseprinzip entsteht eine große interne Verstärkung. Danach wurde dieses Ausleseprinzip auf einer SOI-Struktur angewendet. Dabei werden alle Vorteile eines Hochspannungs- und Hochtemperaturprozesses zusammen mit den Möglichkeiten genutzt, die ein Standard CMOS Prozess zur Integration der Ausleseelektronik auf dem selben Chip erlaubt. Im Rahmen dieser Dissertation wurde darüber hinaus die Möglichkeit untersucht, die Indium-Zinn-Oxid (ITO) Schichten im 0,5µm Standard CMOS Prozess als Gate-Material einzusetzen. Dies bewirkt einen höheren Quantumwirkungsgrad im sichtbaren Wellenlängenbereich, wenn es bei Photogate-Pixel angewandt wird. Im Nah-Infrarot Wellenlängenbereich jedoch bringt es keine Vorteile gegenüber dem standardmäßig verwendeten Polysilizium. Anschließend wurden verschiedene Pixelstrukturen im 0,35µm Standard CMOS Prozess entworfen und simuliert. Dabei wurde gezeigt, dass zumindest theoretisch das Ladungskopplungsprinzip bei den auf „Photogates“ und auf „Buried-Photodioden“ basierenden Strukturen funktioniert

A low-voltage CMOS-compatible time-domain photodetector, device & front end electronics

During the last decades, the usage of silicon photodetectors, both as stand-alone sensor or integrated in arrays, grew tremendously. They are now found in almost any application and any market range, from leisure products to high-end scientific apparatuses, including, among others, industrial, automotive, and medical equipment. The impressive growth in photodetector applications is closely linked to the development of CMOS technology, which now offers inexpensive and efficient analog and digi-tal signal processing capabilities. Detectors are often integrated with their respective front end and application-specific digital circuit on the same silicon die, forming complete systems on chip. In some cases the detector itself is not on the same chip but often part of the same package. However, this trend of co-integration of analog front end and digital circuits complicates the design of the analog part. The ever-decreasing supply voltage and the smaller transistors in advanced processes (which are driven by the development of digital cir-cuits) negatively impact the performance of the analog structures and complicates their design. For photodetector systems, the effect most importantly translates into a degradation of dynamic range and signal-to-noise ratio. One way to circumvent the problem of low supply voltages is to shift the operation from voltage domain to time domain. By doing so, the signal is no longer constrained by the supply rails and analog amplification is avoided. The signal takes the form of a time-based modulation, such as pulse-width modulation or pulse-frequency modulation. Another advantage is that the output signal of a time-domain photodetection system is directly interfaceable with digital circuits. In this work, a new type of CMOS-compatible photodetector displaying intrinsic light-to-time conversion is proposed. Its physical structure consists of a MOS gate interleaved with a PN junction. The MOS structure is acting as a photogate. The depletion region shrinks when photogenerated carriers fill the potential well. At some point, the anode of the PN structure is de-isolated from the rest of the detector and triggers a positive-feedback effect that leads to a very steep current increase through the PN-junction. This translates into a signal of very high amplitude and independent from light-intensity, which can be almost directly interfaced with digital circuits. This simplifies the front end circuit compared to photodiode-based systems. The physical behavior of the device is analyzed with the help of TCAD simulations and simple behavioral and shot-noise models are proposed. The device has been co-integrated with its driver and front end circuit in a standard CMOS process and its characteristics have been measured with a custom-made measurement system. The effect of bias parameters on the performance of the sensor are also analyzed. The limitations of the device are discussed, the most important ones being dark current and linearity. Techno-logical solutions, such as the implementation of the detector on Silicon-on-Insulator technology, are proposed to overcome the limitations. Finally, some application demonstrators have been realized. Other applications that could benefit from the detector are suggested, such as digital applications taking advantage of the latching behavior of the device, and a Photoplethysmography (PPG) system that uses a PLL-based control loop to minimize the emitting LED-current

Spin-on siloxane polymers in image sensor applications

Tässä työssä esitellään siloksaani-pohjaisten spin-on polymeerien tuomia etuja CMOS-kuvakennojen toimintaan. Ensimmäisessä osassa tutustutaan valon perusominaisuuksiin ja kuinka se käyttäytyy kulkiessaan väliaineessa sekä rajapintojen yli. Lisäksi käydään läpi nykyisin yleisimmin käytössä olevien kuvakennojen toimintaa sekä rakennetta. Työn kokeellisessa osuudessa tullaan osoittamaan mitä etuja siloksaani-pohjaisilla polymeereillä on kennojen valmistuksessa tavallisesti käytettyihin eristekerroksiin verrattuna. Työn aikana tutkittiin erityisesti Silecsin valmistamien korkean taitekertoimen spin-on polymeerikalvojen soveltuvuutta kennon valokanavarakenteeseen. Parannukset erityisesti pieniä pikseleitä hyödyntävien CMOS-kuvakennojen kvanttihyötysuhteeseen sekä pikselien väliseen ylikuulumiseen havainnollistetaan sekä optisen mallinnuksen että käytännön mittausten avulla. IBM:n 2.2 µm pikselikoon CMOS-kuvakennossa saavutettiin valokanavarakenteen avulla 24% parannus kvanttihyötysuhteessa ja 19% parannus ylikuulumisessa. Lisäksi työssä arvioidaan matalan taitekertoimen omaavien polymeerikalvojen soveltuvuutta kennojen passivointiin ja heijastuksenestoon. Havaittiin, että mikrolinssin pinnasta syntyviä heijastuksia pystyttiin merkittävästi vähentämään säätämällä kalvon paksuus ja taitekerroin sovellukseen sopivaksi. Lopuksi havainnollistetaan suorakuvioitavien polymeerien tuomia etuja kennon valmistusprosessiin.The feasibility of siloxane based spin-on polymers in a complementary metal oxide semiconductor (CMOS) image sensor application is studied in this thesis. After an introduction to the fundamental characteristics of light and how it behaves when propagating in matter and through interfaces, the basic operation principles of the most commonly used modern image sensors are reviewed. The experimental part of the thesis will demonstrate the improvements achieved in image sensor performance when replacing conventional dielectrics with siloxane based polymers having specifically tuned refractive indices. Results from optical modelling as well as measurement data from fully functional devices are used to demonstrate the enhanced device performance. Silecs' high refractive index spin-on polymers are shown to significantly improve the quantum efficiency and reduce crosstalk of a small pixel size image sensor utilizing a lightpipe structure. Up to 24% quantum efficiency and 19% crosstalk improvement was achieved in an IBM 2.2 µm pixel size sensor when comparing to a conventional structure. Silecs' low refractive index polymer films used as passivation and anti-reflection coatings on the image sensor microlens array were also studied. Lower reflectance from the microlens surface was achieved by properly tuning the overcoat film thickness and refractive index. Additionally, the overcoat provides mechanical protection to the soft microlens material which can result in improved manufacturing yield. Finally, photosensitized siloxane polymers are demonstrated to yield excellent photopatternability with using industry standard lithographic techniques

Miniature high dynamic range time-resolved CMOS SPAD image sensors

Since their integration in complementary metal oxide (CMOS) semiconductor technology in 2003, single photon avalanche diodes (SPADs) have inspired a new era of low cost high integration quantum-level image sensors. Their unique feature of discerning single photon detections, their ability to retain temporal information on every collected photon and their amenability to high speed image sensor architectures makes them prime candidates for low light and time-resolved applications. From the biomedical field of fluorescence lifetime imaging microscopy (FLIM) to extreme physical phenomena such as quantum entanglement, all the way to time of flight (ToF) consumer applications such as gesture recognition and more recently automotive light detection and ranging (LIDAR), huge steps in detector and sensor architectures have been made to address the design challenges of pixel sensitivity and functionality trade-off, scalability and handling of large data rates. The goal of this research is to explore the hypothesis that given the state of the art CMOS nodes and fabrication technologies, it is possible to design miniature SPAD image sensors for time-resolved applications with a small pixel pitch while maintaining both sensitivity and built -in functionality. Three key approaches are pursued to that purpose: leveraging the innate area reduction of logic gates and finer design rules of advanced CMOS nodes to balance the pixel’s fill factor and processing capability, smarter pixel designs with configurable functionality and novel system architectures that lift the processing burden off the pixel array and mediate data flow. Two pathfinder SPAD image sensors were designed and fabricated: a 96 × 40 planar front side illuminated (FSI) sensor with 66% fill factor at 8.25μm pixel pitch in an industrialised 40nm process and a 128 × 120 3D-stacked backside illuminated (BSI) sensor with 45% fill factor at 7.83μm pixel pitch. Both designs rely on a digital, configurable, 12-bit ripple counter pixel allowing for time-gated shot noise limited photon counting. The FSI sensor was operated as a quanta image sensor (QIS) achieving an extended dynamic range in excess of 100dB, utilising triple exposure windows and in-pixel data compression which reduces data rates by a factor of 3.75×. The stacked sensor is the first demonstration of a wafer scale SPAD imaging array with a 1-to-1 hybrid bond connection. Characterisation results of the detector and sensor performance are presented. Two other time-resolved 3D-stacked BSI SPAD image sensor architectures are proposed. The first is a fully integrated 5-wire interface system on chip (SoC), with built-in power management and off-focal plane data processing and storage for high dynamic range as well as autonomous video rate operation. Preliminary images and bring-up results of the fabricated 2mm² sensor are shown. The second is a highly configurable design capable of simultaneous multi-bit oversampled imaging and programmable region of interest (ROI) time correlated single photon counting (TCSPC) with on-chip histogram generation. The 6.48μm pitch array has been submitted for fabrication. In-depth design details of both architectures are discussed

Modelling and characterization of small photosensors in advanced CMOS technologies

The rapid scaling of CMOS technologies and the development of optimized CIS (CMOS Image Sensor) processes for CMOS vision products has not been met by a similar effort in a comprehensive study of the main physical phenomena dominating the behavior of pixels at these technological nodes. This work provides a study of the behaviour of small photodetectors in advanced CMOS technologies in order to evaluate the impact of the geometry on the pixel photoresponse. Several models were developed paying special attention to the peripheral collection. The results suggest that the largest active area no longer necessarily guarantees the optimum response and show the significance of the lateral contribution for small photodiodes. That is, they establish the need to find a trade-off between the active area and the collecting area surrounding the junction to maximize the response. Based on the solution of the two-dimensional steady-state equation in the surroundings of the junction, an analytical model for uniformly illuminated p-n+ junction photodiodes was proposed. It is compact, general and scalable. In order to be used in Computer Aided Design (CAD) tools, the model was implemented in a Hardware Description Language (HDL) and used for circuit simulations to illustrate the potential of the model for the optimization of the pixel performance

A Highly-Sensitive Global-Shutter CMOS Image Sensor with On-Chip Memory For Hundreds of Kilo-Frames Per Second Scientific Experiments

In this work, a highly-sensitive global-shutter CMOS image sensor with on-chip memory that can capture up to 16 frames at speeds higher than 200kfps is presented. The sensor fabricated and tested is a 100 x 100 pixel sensor, and was designed to be expandable to a 1000 x 1000 pixel sensor using the same building blocks and similar architecture. The heart of the sensor is the pixel. The pixel consists of 11 transistors (11T) and 2 MOSFET capacitors. A 6T front-end is followed by a Correlated Double Sampling (CDS) circuitry that includes 2 capacitors and a reset switch. The 4T back-end circuitry consists of a source follower, in-pixel current source and 2 switches. The pixel design is unique because of the following. In a relatively small area, 15.1um x 15.1um, it performs CDS that limits the noise stored in the pixel memories to less than 0.33mV rms and allows the stored value to be read in a single readout. Moreover, it has in-pixel current source, which can be turned OFF when not in use, to remove the dependency of its output voltage to its location in the sensor. Furthermore, the in-pixel capacitors are MOSFET capacitors and do not utilize any space in the upper metal layers, therefore, they can be used exclusively for routing. And at the same time it has a fill factor greater than 40%, which important for high sensitivity. Each pixel is connected to a dedicated memory, which is outside the pixel array and consists of 16 MOSFET capacitors and their access switches (1T1C design). Fifty pixels share a line for their connection to their dedicated memory blocks, and, therefore, the transfer of all the stored pixel values to the on-chip memories happens within 50 clock cycles. This allows capturing consecutive frames at speeds higher than 200 kfps. The total rms noise stored in the memories is 0.4 mV

Radiation Effects on CMOS Active Pixel Image Sensors

Today, Complementary-Metal-Oxide-Semiconductor (CMOS) Image Sensors (CIS), also called Active Pixel Sensors (APS), are the most popular imager technology with several billions manufactured every year. They represent about 90% of the imager market and should exceed 95% in a couple of years. Compared to the main alternative imager technology, the Charge Coupled Device (CCD), CISs have several major benefits such as low-power consumption, high-integration, high speed and the capacity to integrate advanced CMOS functions on-chip (and even inside the pixel). Thanks to the latest technology innovations, CISs are now matching the performances of CCDs in terms of image quality and sensitivity placing them at the forefront even in high-end applications such as digital single-lens reflex, scientific instruments, and machine vision. Thanks to these advantages, CISs are also used in harsh radiation environment for applications such as: space applications, X-ray medical imaging, electron microscopy, nuclear facility monitoring and remote handling (nuclear power plants, nuclear waste repositories, nuclear physics facilities…), particle detection and imaging, military applications etc.. Designing, hardening and testing a sensor for such applications require the understanding of the CIS behavior when exposed to radiation sources. Understanding and improving further the intrinsically good radiation hardness of APS has been a topic of interest since its invention. This interest has been recently growing with the coming of new behaviors brought by the profound evolution of CIS technologies (as discussed throughout this manuscript) compared to the older generation mainstream CMOS processes used in early work. The aim of this chapter is to give an overview of the parasitic effects that can undergo a modern CIS when it is exposed to a high energy particle radiation field

Monolithic electronic-photonic integration in state-of-the-art CMOS processes

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Cataloged from student submitted PDF version of thesis.Includes bibliographical references (p. 388-407).As silicon CMOS transistors have scaled, increasing the density and energy efficiency of computation on a single chip, the off-chip communication link to memory has emerged as the major bottleneck within modern processors. Photonic devices promise to break this bottleneck with superior bandwidth-density and energy-efficiency. Initial work by many research groups to adapt photonic device designs to a silicon-based material platform demonstrated suitable independent performance for such links. However, electronic-photonic integration attempts to date have been limited by the high cost and complexity associated with modifying CMOS platforms suitable for modern high-performance computing applications. In this work, we instead utilize existing state-of-the-art electronic CMOS processes to fabricate integrated photonics by: modifying designs to match the existing process; preparing a design-rule compliant layout within industry-standard CAD tools; and locally-removing the handle silicon substrate in the photonic region through post-processing. This effort has resulted in the fabrication of seven test chips from two major foundries in 28, 45, 65 and 90 nm CMOS processes. Of these efforts, a single die fabricated through a widely available 45nm SOI-CMOS mask-share foundry with integrated waveguides with 3.7 dB/cm propagation loss alongside unmodified electronics with less than 5 ps inverter stage delay serves as a proof-of-concept for this approach. Demonstrated photonic devices include high-extinction carrier-injection modulators, 8-channel wavelength division multiplexing filter banks and low-efficiency silicon germanium photodetectors. Simultaneous electronic-photonic functionality is verified by recording a 600 Mb/s eye diagram from a resonant modulator driven by integrated digital circuits. Initial work towards photonic device integration within the peripheral CMOS flow of a memory process that has resulted in polysilicon waveguide propagation losses of 6.4 dB/cm will also be presented.by Jason S. Orcutt.Ph.D