The 10 to the 8th power bit solid state spacecraft data recorder

The results are summarized of a program to demonstrate the feasibility of Bubble Domain Memory Technology as a mass memory medium for spacecraft applications. The design, fabrication and test of a partially populated 10 to the 8th power Bit Data Recorder using 100 Kbit serial bubble memory chips is described. Design tradeoffs, design approach and performance are discussed. This effort resulted in a 10 to the 8th power bit recorder with a volume of 858.6 cu in and a weight of 47.2 pounds. The recorder is plug reconfigurable, having the capability of operating as one, two or four independent serial channel recorders or as a single sixteen bit byte parallel input recorder. Data rates up to 1.2 Mb/s in a serial mode and 2.4 Mb/s in a parallel mode may be supported. Fabrication and test of the recorder demonstrated the basic feasibility of Bubble Domain Memory technology for such applications. Test results indicate the need for improvement in memory element operating temperature range and detector performance

Laminated ferrite memory system

Feasibility study of random access laminated ferrite memory system for spacecraft us

Reliable miniature spaceborne memory Interim engineering report, 19 Nov. 1964 - 26 Jul. 1965

Reliable miniature spaceborne memory system design, and testing of breadboard version of circuits and memory plan

Digital control for automating feed distribution in feedlots

An investigation was conducted to determine the feasibility of automatic controls to automate feed distribution in feedlots. The control approach was restricted to compatibility with conventional feeding equipment. Input control signals were taken to originate from commonly available mechanical and electronic sensors. The control system was implemented with standard digital logic components;The proposed digital control system is based on a railguided, self-propelled automatic vehicle capable of delivering feed sequentially to 255 pens located on both sides of a single feeding path. A manual, closed-loop control system consisting of the following functions was developed: (1) pen identification, (2) initialization control, (3) feeding mode, (4) exit from feeding mode, (5) re-entry into feeding mode, (6) end of feeding cycle, (7) ground drive and conveyor control, (8) interface and auto/manual mode, (9) monitoring of automated system and (10) data and failure display and alarm. The control system allows either automatic or manual operation of the feeding vehicle. Digital electronic circuits capable of implementing the desired control functions were designed;The feeding cycle is manually initiated and automatically terminated when feed has been delivered to all pens requiring feed. It can be partially programmed to enable feed delivery to sections of the feedlot. Two feed rations can be delivered. The feeding status of each pen is recorded. The pen feed rations are stored in reprogrammable memories;The operation of the automated feeding system is based on the automatic identification of the feedlot pens. The number assigned to a pen is coded, using binary pulse-code modulation. Frequency-shift keying is used to transmit the coded number. The received coded number is recovered by specialized communication circuits and then validated;The control system monitors the vehicle components and the major electronic circuits to detect failures, prevent damage and produce a safe operation. Furthermore, it incorporates safety sensors and logic circuitry to meet the basic safety requirements pertaining to automated vehicles;The proposed automated feed distribution system for feedlots is expected to: (1) reduce management requirements through automatic distribution of feed to cattle raised in pens, (2) increase efficiency of feeding operation by eliminating time losses associated with secondary feed transfer, (3) eliminate damage to feedbunks through positive guidance of the vehicle by rails, and (4) save energy by eliminating secondary feed transfer

Technical Design Report for the PANDA Micro Vertex Detector

This document illustrates the technical layout and the expected performance of the Micro Vertex Detector (MVD) of the PANDA experiment. The MVD will detect charged particles as close as possible to the interaction zone. Design criteria and the optimisation process as well as the technical solutions chosen are discussed and the results of this process are subjected to extensive Monte Carlo physics studies. The route towards realisation of the detector is outlined

Null Convention Logic applications of asynchronous design in nanotechnology and cryptographic security

This dissertation presents two Null Convention Logic (NCL) applications of asynchronous logic circuit design in nanotechnology and cryptographic security. The first application is the Asynchronous Nanowire Reconfigurable Crossbar Architecture (ANRCA); the second one is an asynchronous S-Box design for cryptographic system against Side-Channel Attacks (SCA). The following are the contributions of the first application: 1) Proposed a diode- and resistor-based ANRCA (DR-ANRCA). Three configurable logic block (CLB) structures were designed to efficiently reconfigure a given DR-PGMB as one of the 27 arbitrary NCL threshold gates. A hierarchical architecture was also proposed to implement the higher level logic that requires a large number of DR-PGMBs, such as multiple-bit NCL registers. 2) Proposed a memristor look-up-table based ANRCA (MLUT-ANRCA). An equivalent circuit simulation model has been presented in VHDL and simulated in Quartus II. Meanwhile, the comparison between these two ANRCAs have been analyzed numerically. 3) Presented the defect-tolerance and repair strategies for both DR-ANRCA and MLUT-ANRCA. The following are the contributions of the second application: 1) Designed an NCL based S-Box for Advanced Encryption Standard (AES). Functional verification has been done using Modelsim and Field-Programmable Gate Array (FPGA). 2) Implemented two different power analysis attacks on both NCL S-Box and conventional synchronous S-Box. 3) Developed a novel approach based on stochastic logics to enhance the resistance against DPA and CPA attacks. The functionality of the proposed design has been verified using an 8-bit AES S-box design. The effects of decision weight, bitstream length, and input repetition times on error rates have been also studied. Experimental results shows that the proposed approach enhances the resistance to against the CPA attack by successfully protecting the hidden key --Abstract, page iii

Conceptual study of a micrometeoroid deep space satellite. volume i- summary, development plan, pricing final report

Satellite design for deep space micrometeoroid study - summary, development plan, and cost

Voyager spacecraft. Volume V - Alternate designs, subsystems considerations Study report, phase IA

Telecommunication, propulsion, control, electric, and mechanical subsystems design for Voyager spacecraf