A survey of carbon nanotube interconnects for energy efficient integrated circuits

This article is a review of the state-of-art carbon nanotube interconnects for Silicon application with respect to the recent literature. Amongst all the research on carbon nanotube interconnects, those discussed here cover 1) challenges with current copper interconnects, 2) process & growth of carbon nanotube interconnects compatible with back-end-of-line integration, and 3) modeling and simulation for circuit-level benchmarking and performance prediction. The focus is on the evolution of carbon nanotube interconnects from the process, theoretical modeling, and experimental characterization to on-chip interconnect applications. We provide an overview of the current advancements on carbon nanotube interconnects and also regarding the prospects for designing energy efficient integrated circuits. Each selected category is presented in an accessible manner aiming to serve as a survey and informative cornerstone on carbon nanotube interconnects relevant to students and scientists belonging to a range of fields from physics, processing to circuit design

Electrical and Structural Analysis of CNT-Metal Contacts in Via Interconnects

Vertically aligned carbon nanotubes grown by plasmaenhanced chemical vapor deposition offer a potentially suitable material for via interconnects in next-generation integrated circuits. Key performance-limiting factors include high contact resistance and low carbon nanotube packing density, which fall short of meeting the requirements delineated in the ITRS roadmap for interconnects. For individual carbon nanotube s, contact resistance is a major performance hurdle since it is the dominant component of carbon nanotube interconnect resistance, even in the case of vertically aligned carbon nanotube arrays. In this study, we correlate the carbon nanotube-metal interface nanostructure to their electrical properties in order to elucidate growth parameters that can lead to high density and low contact resistance and resistivity

Carbon Nanotube Interconnects for End-of-Roadmap Semiconductor Technology Nodes

Advances in semiconductor technology due to aggressive downward scaling of on-chip feature sizes have led to rapid rises in resistivity and current density of interconnect conductors. As a result, current interconnect materials, Cu and W, are subject to performance and reliability constraints approaching or exceeding their physical limits. Therefore, alternative materials such as nanocarbons, metal silicides, and Ag nanowires are actively considered as potential replacements to meet such constraints. Among nanocarbons, carbon nanotube (CNT) is among the leading replacement candidate for on-chip interconnect vias due to its high aspect-ratio nanostructure and superior currentcarrying capacity to those of Cu, W, and other potential candidates. However, contact resistance of CNT with metal is a major bottleneck in device functionalization. To meet the challenge posed by contact resistance, several techniques are designed and implemented. First, the via fabrication and CNT growth processes are developed to increase the CNT packing density inside via and to ensure no CNT growth on via sidewalls. CNT vias with cross-sections down to 40 nm 40 nm are fabricated, which have linewidths similar to those used for on-chip interconnects in current integrated circuit manufacturing technology nodes. Then the via top contact is metallized to increase the total CNT area interfacing with the contact metal and to improve the contact quality and reproducibility. Current-voltage characteristics of individual fabricated CNT vias are measured using a nanoprober and contact resistance is extracted with a first-reported contact resistance extraction scheme for 40 nm linewidth. Based on results for 40 nm and 60 nm top-contact metallized CNT vias, we demonstrate that not only are their current-carrying capacities two orders of magnitude higher than their Cu and W counterparts, they are enhanced by reduced via resistance due to contact engineering. While the current-carrying capacities well exceed those projected for end-of-roadmap technology nodes, the via resistances remain a challenge to replace Cu and W, though our results suggest that further innovations in contact engineering could begin to overcome such challenge

Tuning Electrical Conductivity of CNT-PDMS Nanocomposites for Flexible Electronic Applications

This paper presents a study into the electrical conductivity of multi-wall carbon nanotube-polydimethylsiloxane (MWNT-PDMS) nanocomposite and their dependence on the filler concentration. It is observed that the electrical conductivity of the composites can be tailored by altering the filler concentration. Accordingly, the nanocomposites with filler weight ratio ranging from 1% to 8% were prepared and tested. Finally, the significance of results presented here for flexible pressure sensors and stretchable interconnects for electronic skin applications have been discussed

Carbon Nanotube Interconnect Modeling for Very Large Scale Integrated Circuits

In this research, we have studied and analyzed the physical and electrical properties of carbon nanotubes. Based on the reported models for current transport behavior in non-ballistic CNT-FETs, we have built a dynamic model for non-ballistic CNT-FETs. We have also extended the surface potential model of a non-ballistic CNT-FET to a ballistic CNT-FET and developed a current transport model for ballistic CNT-FETs. We have studied the current transport in metallic carbon nanotubes. By considering the electron-electron interactions, we have modified two-dimensional fluid model for electron transport to build a semi-classical one-dimensional fluid model to describe the electron transport in carbon nanotubes, which is regarded as one-dimensional system. Besides its accuracy compared with two-dimensional fluid model and Lüttinger liquid theory, one-dimensional fluid model is simple in mathematical modeling and easier to extend for electronic transport modeling of multi-walled carbon nanotubes and single-walled carbon nanotube bundles as interconnections. Based on our reported one-dimensional fluid model, we have calculated the parameters of the transmission line model for the interconnection wires made of single-walled carbon nanotube, multi-walled carbon nanotube and single-walled carbon nanotube bundle. The parameters calculated from these models show close agreements with experiments and other proposed models. We have also implemented these models to study carbon nanotube for on-chip wire inductors and it application in design of LC voltage-controlled oscillators. By using these CNT-FET models and CNT interconnects models, we have studied the behavior of CNT based integrated circuits, such as the inverter, ring oscillator, energy recovery logic; and faults in CNT based circuits

Carbon nanotubes on graphene: Electrical and interfacial properties

An integrated circuit (IC) consists of copper (Cu) and tungsten (W) interconnects to facilitate conduction among its components such as transistors, resistors, and capacitors. As the minimum feature size in IC technology continues to scale downward into the sub-20 nm regime, interconnects are faced with performance and reliability challenges arising from increased resistance and electromigration, respectively [1]. To partially mitigate such challenges, our project aims at studying a structure as a potential replacement for Cu and W, formed by growing carbon nanotubes (CNTs) directly onto graphene, and investigating the resulting electrical and interfacial properties. Various CNT/Graphene structures are fabricated using sputtered iron (Fe), cobalt (Co), or nickel (Ni) catalyst films and subsequent thermal chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD) processes for CNT growth. The objective of this research is to assess the viability of CNTs directly grown on graphene as a functional alternative to Cu and W interconnects in integrated circuits. Using Co as a catalyst for CNT growth with a thermal CVD process, we have succeeded in creating a conductive all-carbon 3D interconnect structure

Modeling of Thermally Aware Carbon Nanotube and Graphene Based Post CMOS VLSI Interconnect

This work studies various emerging reduced dimensional materials for very large-scale integration (VLSI) interconnects. The prime motivation of this work is to find an alternative to the existing Cu-based interconnect for post-CMOS technology nodes with an emphasis on thermal stability. Starting from the material modeling, this work includes material characterization, exploration of electronic properties, vibrational properties and to analyze performance as a VLSI interconnect. Using state of the art density functional theories (DFT) one-dimensional and two-dimensional materials were designed for exploring their electronic structures, transport properties and their circuit behaviors. Primarily carbon nanotube (CNT), graphene and graphene/copper based interconnects were studied in this work. Being reduced dimensional materials the charge carriers in CNT(1-D) and in graphene (2-D) are quantum mechanically confined as a result of this free electron approximation fails to explain their electronic properties. For same reason Drude theory of metals fails to explain electronic transport phenomena. In this work Landauer transport theories using non-equilibrium Green function (NEGF) formalism was used for carrier transport calculation. For phonon transport studies, phenomenological Fourier’s heat diffusion equation was used for longer interconnects. Semi-classical BTE and Landauer transport for phonons were used in cases of ballistic phonon transport regime. After obtaining self-consistent electronic and thermal transport coefficients, an equivalent circuit model is proposed to analyze interconnects’ electrical performances. For material studies, CNTs of different variants were analyzed and compared with existing copper based interconnects and were found to be auspicious contenders with integrational challenges. Although, Cu based interconnect is still outperforming other emerging materials in terms of the energy-delay product (1.72 fJ-ps), considering the electromigration resistance graphene Cu hybrid interconnect proposed in this dissertation performs better. Ten times more electromigration resistance is achievable with the cost of only 30% increase in energy-delay product. This unique property of this proposed interconnect also outperforms other studied alternative materials such as multiwalled CNT, single walled CNT and their bundles

電気・熱伝導促進を目指したカーボンナノチューブ高密度配列の成長技術の開発

学位の種別: 課程博士審査委員会委員 : （主査）東京大学准教授 三好 明, 東京大学名誉教授 山口 由岐夫, 東京大学教授 大久保 達也, 東京大学准教授 片山 正士, 東京大学教授 丸山 茂夫, 早稲田大学教授 野田 優University of Tokyo(東京大学

Process Optimization for Carbon Nanotubes-On-Graphene Fabrication

Because of their superior thermal and electrical properties, carbon nanotubes (CNTs) and graphene (Gr) are promising candidates to replace copper and tungsten as interconnect materials in the most advanced integrated circuit technologies. We explore a three-dimensional all-carbon interconnect structure, consisting of vertically aligned CNTs grown directly on multi-layer graphene (MLG). The objective is to grow the CNTs with little or no damage to the graphene underlayer. We start with fabricating test structures using both plasma enhanced chemical vapor deposition (PECVD) and thermal CVD throughout the CNT growth process to confirm the results of previous work of our research group. We then proceed to design a process to grow CNTs using PECVD in order to achieve a test structure with not only vertically aligned CNTs, but also a conductive graphene underlayer. In order to achieve this, we vary the plasma conditions within the reactor during the CNT growth process and analyze the fabricated test structure using a scanning electron microscope (SEM) and a wafer probe station. Through our analysis we are able to determine the viability of our designed process. We are able to produce a test structure with partially aligned CNTs and an intact graphene underlayer by lowering the DC voltage of the plasma used in the PECVD process. As a result, we find that resistance of the sample is comparable to that of plain graphene. Three-dimensional all-carbon nanostructures such as the ones fabricated in our project can lead to functionalization of such structures as building blocks for future on-chip interconnects