Optimization techniques for high-performance digital circuits

The relentless push for high performance in custom dig-ital circuits has led to renewed emphasis on circuit opti-mization or tuning. The parameters of the optimization are typically transistor and interconnect sizes. The de-sign metrics are not just delay, transition times, power and area, but also signal integrity and manufacturability. This tutorial paper discusses some of the recently pro-posed methods of circuit optimization, with an emphasis on practical application and methodology impact. Circuit optimization techniques fall into three broad categories. The rst is dynamic tuning, based on time-domain simulation of the underlying circuit, typically combined with adjoint sensitivity computation. These methods are accurate but require the specication of in-put signals, and are best applied to small data- ow cir-cuits and \cross-sections " of larger circuits. Ecient sensitivity computation renders feasible the tuning of cir-cuits with a few thousand transistors. Second, static tuners employ static timing analysis to evaluate the per-formance of the circuit. All paths through the logic are simultaneously tuned, and no input vectors are required. Large control macros are best tuned by these methods. However, in the context of deep submicron custom de-sign, the inaccuracy of the delay models employed by these methods often limits their utility. Aggressive dy-namic or static tuning can push a circuit into a precip-itous corner of the manufacturing process space, which is a problem addressed by the third class of circuit op-timization tools, statistical tuners. Statistical techniques are used to enhance manufacturability or maximize yield. In addition to surveying the above techniques, topics such as the use of state-of-the-art nonlinear optimization methods and special considerations for interconnect siz-ing, clock tree optimization and noise-aware tuning will be brie y considered.

Expansion of CMOS array design techniques

The important features of the multiport (double entry) automatic placement and routing programs for standard cells are described. Measured performance and predicted performance were compared for seven CMOS/SOS array types and hybrids designed with the high speed CMOS/SOS cell family. The CMOS/SOS standard cell data sheets are listed and described

Design techniques for high performance asynchronous arithmetic operators

High performance asynchronous arithmetic operator design techniques are proposed, which adopt some of the techniques commonly used in synchronous systems such as fast precharged logic and efficient latch design, while maintaining the features of localized and elastic pipelining control inherent in asynchronous design. A pipelined sixteen bit multiplier designed using these techniques is presented and its performance compared with several previously reported asynchronous and synchronous designs

High performance circuit techniques for neural front-end design in 65nm CMOS

Integrated low noise neural amplifiers become recently practical in CMOS technologies. In this paper, a low noise OTA technique has been proposed while keeping the power consumption constant. A capacitive feedback, ac coupled 46dB amplifier with high pass cutoff frequency close to the 90Hz has been achieved. The proposed amplifier has been implemented in 65nm CMOS technology; at room temperature circuit consumes 323uA current from 1.2V power supply. The circuit occupies 2627um 2 silicon area