Removal of nitrogen pollutant from domestic wastewater

Water as a medium for waste transport would be easily contaminated by human activities. Many methods have been proposed to treat contaminated water to protect human health and biodiversity (Z. Daud et al., 2017). Due to upgrade the existing wastewater treatment plant facilities, the typically advanced technologies have been proposed to remove many types of pollutant, effectively (Tchobanoglous, Burton, & Stensel, 2004). The development of wastewater treatment plant needs to be considered leading economic indicators to have low operational and maintenance costs (Lewandowski, 2015; Shammas, Wang, & Wu, 2009). Aerobic digestion (AD) has been known since 1950 as biological wastewater treatment process to treat wastewater by removing the pollutants for instance colloids, organic compounds and suspended solids to avoid the excessive pollutants released into the receiving water (Shammas and Wang, 2007)

Power-efficient design of 16-bit mixed-operand multipliers

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.Includes bibliographical references (p. 53).Multiplication is an expensive and slow arithmetic operation, which plays an important role in many DSP algorithms. It usually lies in the critical-delay paths, having an effect on performance of the system as well as consuming large power. Consequently, significant improvements in both power and performance can be achieved in the overall DSP system by carefully designing and optimizing power and performance of the multiplier. This thesis explores several circuit-level techniques for power-efficiently designing multipliers, including supply voltage reduction, efficient multiplication algorithms, low power circuit logic styles, and transistor sizing using dynamic and static tuners. Based on these techniques, several 16-bit multipliers have been successfully designed and implemented in 0.13[micro]m CMOS technology at the supply voltage of 1.5V and 0.9V. The multipliers are modified to handle multiplications of two 16-bit operands in which each can be either signed magnitude or two's complement formats. Examining power-performance characteristics of these multipliers reveals that both array and tree structures are feasible solutions for designing 16-bit multipliers, and complementary CMOS and single-ended CPL-TG logics are promising candidates for power-efficient design. The appropriate choices of structures and logic styles depend on power and performance constraints of the particular design.by Sataporn Pornpromlikit.M.Eng

Design techniques for high performance asynchronous arithmetic operators

High performance asynchronous arithmetic operator design techniques are proposed, which adopt some of the techniques commonly used in synchronous systems such as fast precharged logic and efficient latch design, while maintaining the features of localized and elastic pipelining control inherent in asynchronous design. A pipelined sixteen bit multiplier designed using these techniques is presented and its performance compared with several previously reported asynchronous and synchronous designs