1,182 research outputs found
Analogue to Digital and Digital to Analogue Converters (ADCs and DACs): A Review Update
This is a review paper updated from that presented for CAS 2004. Essentially,
since then, commercial components have continued to extend their performance
boundaries but the basic building blocks and the techniques for choosing the
best device and implementing it in a design have not changed. Analogue to
digital and digital to analogue converters are crucial components in the
continued drive to replace analogue circuitry with more controllable and less
costly digital processing. This paper discusses the technologies available to
perform in the likely measurement and control applications that arise within
accelerators. It covers much of the terminology and 'specmanship' together with
an application-oriented analysis of the realisable performance of the various
types. Finally, some hints and warnings on system integration problems are
given.Comment: 15 pages, contribution to the 2014 CAS - CERN Accelerator School:
Power Converters, Baden, Switzerland, 7-14 May 201
Robust low power CMOS methodologies for ISFETs instrumentation
I have developed a robust design methodology in a 0.18 [Mu]m commercial CMOS process
to circumvent the performance issues of the integrated Ions Sensitive Field Effect Transistor
(ISFET) for pH detection. In circuit design, I have developed frequency domain signal
processing, which transforms pH information into a frequency modulated signal. The
frequency modulated signal is subsequently digitized and encoded into a bit-stream of data.
The architecture of the instrumentation system consists of a) A novel front-end averaging
amplifier to interface an array of ISFETs for converting pH into a voltage signal, b) A high
linear voltage controlled oscillator for converting the voltage signal into a frequency
modulated signal, and c) Digital gates for digitizing and differentiating the frequency
modulated signal into an output bit-stream. The output bit stream is indistinguishable to a 1st
order sigma delta modulation, whose noise floor is shaped by +20dB/decade.
The fabricated instrumentation system has a dimension of 1565 [Mu] m 1565 [Mu] m. The chip
responds linearly to the pH in a chemical solution and produces a digital output, with up to an
8-bit accuracy. Most importantly, the fabricated chips do not need any post-CMOS
processing for neutralizing any trapped-charged effect, which can modulate on-chip ISFETs’
threshold voltages into atypical values. As compared to other ISFET-related works in the
literature, the instrumentation system proposed in this thesis can cope with the mismatched
ISFETs on chip for analogue-to-digital conversions. The design methodology is thus very
accurate and robust for chemical sensing
Multi-stage noise shaping (MASH) delta-sigma modulators for wideband and multi-standard applications
Imperial Users onl
Ultra-low noise, high-frame rate readout design for a 3D-stacked CMOS image sensor
Due to the switch from CCD to CMOS technology, CMOS based image sensors have become
smaller, cheaper, faster, and have recently outclassed CCDs in terms of image quality. Apart
from the extensive set of applications requiring image sensors, the next technological
breakthrough in imaging would be to consolidate and completely shift the conventional CMOS
image sensor technology to the 3D-stacked technology. Stacking is recent and an innovative
technology in the imaging field, allowing multiple silicon tiers with different functions to be
stacked on top of each other. The technology allows for an extreme parallelism of the pixel
readout circuitry. Furthermore, the readout is placed underneath the pixel array on a 3D-stacked
image sensor, and the parallelism of the readout can remain constant at any spatial resolution of
the sensors, allowing extreme low noise and a high-frame rate (design) at virtually any sensor
array resolution.
The objective of this work is the design of ultra-low noise readout circuits meant for 3D-stacked
image sensors, structured with parallel readout circuitries. The readout circuit’s key
requirements are low noise, speed, low-area (for higher parallelism), and low power.
A CMOS imaging review is presented through a short historical background, followed by the
description of the motivation, the research goals, and the work contributions. The fundamentals
of CMOS image sensors are addressed, as a part of highlighting the typical image sensor features,
the essential building blocks, types of operation, as well as their physical characteristics and their
evaluation metrics. Following up on this, the document pays attention to the readout circuit’s
noise theory and the column converters theory, to identify possible pitfalls to obtain sub-electron
noise imagers. Lastly, the fabricated test CIS device performances are reported along with
conjectures and conclusions, ending this thesis with the 3D-stacked subject issues and the future
work. A part of the developed research work is located in the Appendices.Devido à mudança da tecnologia CCD para CMOS, os sensores de imagem em CMOS tornam se mais pequenos, mais baratos, mais rápidos, e mais recentemente, ultrapassaram os sensores
CCD no que respeita à qualidade de imagem. Para além do vasto conjunto de aplicações que
requerem sensores de imagem, o prĂłximo salto tecnolĂłgico no ramo dos sensores de imagem Ă©
o de mudar completamente da tecnologia de sensores de imagem CMOS convencional para a
tecnologia “3D-stacked”. O empilhamento de chips é relativamente recente e é uma tecnologia
inovadora no campo dos sensores de imagem, permitindo vários planos de silĂcio com diferentes
funções poderem ser empilhados uns sobre os outros. Esta tecnologia permite portanto, um
paralelismo extremo na leitura dos sinais vindos da matriz de pĂxeis. AlĂ©m disso, num sensor de
imagem de planos de silĂcio empilhados, os circuitos de leitura estĂŁo posicionados debaixo da
matriz de pĂxeis, sendo que dessa forma, o paralelismo pode manter-se constante para qualquer
resolução espacial, permitindo assim atingir um extremo baixo ruĂdo e um alto debito de
imagens, virtualmente para qualquer resolução desejada.
O objetivo deste trabalho Ă© o de desenhar circuitos de leitura de coluna de muito baixo ruĂdo,
planeados para serem empregues em sensores de imagem “3D-stacked” com estruturas
altamente paralelizadas. Os requisitos chave para os circuitos de leitura sĂŁo de baixo ruĂdo,
rapidez e pouca área utilizada, de forma a obter-se o melhor rácio.
Uma breve revisĂŁo histĂłrica dos sensores de imagem CMOS Ă© apresentada, seguida da
motivação, dos objetivos e das contribuições feitas. Os fundamentos dos sensores de imagem
CMOS sĂŁo tambĂ©m abordados para expor as suas caracterĂsticas, os blocos essenciais, os tipos
de operação, assim como as suas caracterĂsticas fĂsicas e suas mĂ©tricas de avaliação. No
seguimento disto, especial atenção Ă© dada Ă teoria subjacente ao ruĂdo inerente dos circuitos de
leitura e dos conversores de coluna, servindo para identificar os possĂveis aspetos que dificultem
atingir a tĂŁo desejada performance de muito baixo ruĂdo. Por fim, os resultados experimentais
do sensor desenvolvido sĂŁo apresentados junto com possĂveis conjeturas e respetivas conclusões,
terminando o documento com o assunto de empilhamento vertical de camadas de silĂcio, junto
com o possĂvel trabalho futuro
A Mixed-Signal Feed-Forward Neural Network Architecture Using A High-Resolution Multiplying D/A Conversion Method
Artificial Neural Networks (ANNs) are parallel processors capable of learning from a set of sample data using a specific learning rule. Such systems are commonly used in applications where human brain may surpass conventional computers such as image processing, speech/character recognition, intelligent control and robotics to name a few. In this thesis, a mixed-signal neural network architecture is proposed employs a high resolution Multiplying Digital to Analog Converter (MDAC) designed using Delta Sigma Modulation (DSM). To reduce chip are, multiplexing is used in addition to analog implementation of arithmetic operations. This work employs a new method for filtering the high bit-rate signals using neurons nonlinear transfer function already existing in the network. Therefore, a configuration of a few MOS transistors are replacing the large resistors required to implement the low-pass filter in the network. This configuration noticeably decreases the chip area and also makes multiplexing feasible for hardware implementation
Design of a Class-D RF power amplifier in CMOS technology
In this thesis an RF Class-D Power Amplifier is presented. The analysis of the Class-D
amplifier considering ideal components has shown that the drain efficiency of 100% can
be achieved. The output power and the drain efficiency are degraded by the internal
resistance of each component. A driver is used to drive the gate capacitances of the Class-D amplifier. Both driver and amplifier are implemented with CMOS inverters. The size of the inverters in the driver is scaled down by a factor of 3 relatively to the preceding stage.
The first being the inverter of the Class-D amplifier. At the output a 3rd order Butterworth bandpass filter is implemented. A non-ideal analysis of the Class-D amplifier is performed to create a base model which is used to aid in the design of the circuit.
The RF Class-D Power Amplifier with the operation frequency of 2.4GHz was implemented with standard 130 nm CMOS technology. Two simulations were taken into
account considering ideal and pre-layout components in the output filter. The following
results were obtained when using ideal components: the output power of 6.91 dBm, the
drain efficiency of 40% and the overall efficiency of 23%. Using pre-layout components the results were the following: the output power of 0.317 dBm the drain and overall efficiency of 8.6% and 4.9%, respectively
Performance evaluation of currently available VLSI implementations satisfying U-interface requirements for an ISDN in South Africa.
A project report submitted to the Faculty of Engineering, University of the
Witwatersrand, Johannesburg, in partial fulfilment of the requirements for the
degree of Master of Science in Engineering.This project report examines the performance of three VLSI U-interface implementations
satisfying the requirements of Basic Access on an ISDN.
The systems evaluated are the Intel 89120,Siemens PEB2090 and STC DSP144, operating
on 2BIQ, MMS4J and SU32 line codes respectively.
Before evaluating the three abovementioned systems, a review of the underlying principles
of U-interface technology is presented. Included in the review are aspects of transmission
line theory, line coding, echo-cancellation, decision feedback equalisation, and pulse density
modulation. The functional specifications of the three systems are then presented followed
by a practical evaluation of each system.
As an aid to testing the transmission systems, an evaluation board has been designed and
built. The latter provides the necessary functionality to correctly activate each system, as
well as the appropriate interfacing requirements for the error-rate tester.
The U-interface transmission systems are evaluated on a number of test-loops, comprising
sections of cable varying in length and gauge. Additionally, impairments are injected into
data-carrying cables, in order to test the performance of each system in the presence of
noise. The results of each test are recorded and analysed.
Finally, a recommendation is made in favour of the 2BIQ U-interface. It is shown to offer
superior transmission performance, at the expense of a slightly higher transmit-power level.Andrew Chakane 201
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