DFT and BIST of a multichip module for high-energy physics experiments

Engineers at Politecnico di Torino designed a multichip module for high-energy physics experiments conducted on the Large Hadron Collider. An array of these MCMs handles multichannel data acquisition and signal processing. Testing the MCM from board to die level required a combination of DFT strategie

Testing Embedded Memories in Telecommunication Systems

Extensive system testing is mandatory nowadays to achieve high product quality. Telecommunication systems are particularly sensitive to such a requirement; to maintain market competitiveness, manufacturers need to combine reduced costs, shorter life cycles, advanced technologies, and high quality. Moreover, strict reliability constraints usually impose very low fault latencies and a high degree of fault detection for both permanent and transient faults. This article analyzes major problems related to testing complex telecommunication systems, with particular emphasis on their memory modules, often so critical from the reliability point of view. In particular, advanced BIST-based solutions are analyzed, and two significant industrial case studies presente

Adaptive market hypothesis

Purpose: To investigate the implications of the Addaptive Market Hypothesis (AMH) on Turkish stock exchange market (Borsa Istanbul) indices as an emerging economy. BIST-100, BIST-30 and BIST-All indices are subjected to the analyses for the period between January 2002 and April 2017. Design/Methodology/Approach: Two-year rolling windows and daily test values were calculated by using linear methods (Variance Ratio Test) and nonlinear methods (BDS test) to investigate the market efficiency. Findings: According to the Variance Ratio Test results, index returns are unpredictable, that is, the market is efficient, while the results of nonlinear analysis show the existence of adaptive market hypothesis. In particular, all three indices display efficiency in the 2013-2016 period implying that returns were not predictable in this period. The results of the non-linear analysis show that the market is efficient from time to time and sometimes deviates from efficiency, indicating the validity of the adaptive market hypothesis in Borsa Istanbul. Practical Implications: The changes in the market efficiency from time to time should be considered while taking important investment decisions. Moreover, according to AMH, since trends, panics, bubbles and crashes exist in the market, arbitrage opportunities arise time to time, and market timing is an important issue to catch the profit opportunities. Therefore, as a further study, matching the important events with the efficiency of the market could provide more insights about timing the market. Originality/Value: To the best of authors’ knowledge, this is the first comprehensive study that examines the index based AMH in Borsa Istanbul. This study is believed to contribute to the literature by giving insights about the evolution of market efficiency in Turkey.peer-reviewe

A low-speed BIST framework for high-performance circuit testing

Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a design-for-test methodology such that high performance devices can be tested on relatively low performance testers. In addition, a BIST framework is discussed based on this methodology. Various implementation aspects of this technique are also addresse

An On-line BIST RAM Architecture with Self Repair Capabilities

The emerging field of self-repair computing is expected to have a major impact on deployable systems for space missions and defense applications, where high reliability, availability, and serviceability are needed. In this context, RAM (random access memories) are among the most critical components. This paper proposes a built-in self-repair (BISR) approach for RAM cores. The proposed design, introducing minimal and technology-dependent overheads, can detect and repair a wide range of memory faults including: stuck-at, coupling, and address faults. The test and repair capabilities are used on-line, and are completely transparent to the external user, who can use the memory without any change in the memory-access protocol. Using a fault-injection environment that can emulate the occurrence of faults inside the module, the effectiveness of the proposed architecture in terms of both fault detection and repairing capability was verified. Memories of various sizes have been considered to evaluate the area-overhead introduced by this proposed architectur

Testing high resolution SD ADC’s by using the noise transfer function

A new solution to improve the testability of high resolution SD Analogue to Digital Converters (SD ADC’s) using the quantizer input as test node is described. The theoretical basis for the technique is discussed and results from high level simulations for a 16 bit, 4th order, audio ADC are presented. The analysis demonstrates the potential to reduce the computational effort associated with test response analysis versus conventional techniques