Towards a triple mode common operator FFT for Software Radio systems

International audienceA scenario to design a Triple Mode FFT is addressed. Based on a Dual Mode FFT structure, we present a methodology to reach a triple mode FFT operator (TMFFT) able to operate over three different fields: complex number domain C, Galois Fields GF(Ft) and GF(2m). We propose a reconfigurable Triple mode Multiplier that constitutes the core of the Butterflybased FFT. A scalable and flexible unit for the polynomial reduction needed in the GF(2m) multiplication is also proposed. An FPGA implementation of the proposed multiplier is given and the measures show a gain of 18%in terms of performance-to-cost ratio compared to a "Velcro" approach where two self-contained operators are implemented separately

Design of microprocessor-based hardware for number theoretic transform implementation

Number Theoretic Transforms (NTTs) are defined in a finite ring of integers Z (_M), where M is the modulus. All the arithmetic operations are carried out modulo M. NTTs are similar in structure to DFTs, hence fast FFT type algorithms may be used to compute NTTs efficiently. A major advantage of the NTT is that it can be used to compute error free convolutions, unlike the FFT it is not subject to round off and truncation errors. In 1976 Winograd proposed a set of short length DFT algorithms using a fewer number of multiplications and approximately the same number of additions as the Cooley-Tukey FFT algorithm. This saving is accomplished at the expense of increased algorithm complexity. These short length DFT algorithms may be combined to perform longer transforms. The Winograd Fourier Transform Algorithm (WFTA) was implemented on a TMS9900 microprocessor to compute NTTs. Since multiplication conducted modulo M is very time consuming a special purpose external hardware modular multiplier was designed, constructed and interfaced with the TMS9900 microprocessor. This external hardware modular multiplier allowed an improvement in the transform execution time. Computation time may further be reduced by employing several microprocessors. Taking advantage of the inherent parallelism of the WFTA, a dedicated parallel microprocessor system was designed and constructed to implement a 15-point WFTA in parallel. Benchmark programs were written to choose a suitable microprocessor for the parallel microprocessor system. A master or a host microprocessor is used to control the parallel microprocessor system and provides an interface to the outside world. An analogue to digital (A/D) and a digital to analogue (D/A) converter allows real time digital signal processing

Implementation and analysis of the generalised new Mersenne number transforms for encryption

PhD ThesisEncryption is very much a vast subject covering myriad techniques to conceal and safeguard data and communications. Of the techniques that are available, methodologies that incorporate the number theoretic transforms (NTTs) have gained recognition, specifically the new Mersenne number transform (NMNT). Recently, two new transforms have been introduced that extend the NMNT to a new generalised suite of transforms referred to as the generalised NMNT (GNMNT). These two new transforms are termed the odd NMNT (ONMNT) and the odd-squared NMNT (O2NMNT). Being based on the Mersenne numbers, the GNMNTs are extremely versatile with respect to vector lengths. The GNMNTs are also capable of being implemented using fast algorithms, employing multiple and combinational radices over one or more dimensions. Algorithms for both the decimation-in-time (DIT) and -frequency (DIF) methodologies using radix-2, radix-4 and split-radix are presented, including their respective complexity and performance analyses. Whilst the original NMNT has seen a significant amount of research applied to it with respect to encryption, the ONMNT and O2NMNT can utilise similar techniques that are proven to show stronger characteristics when measured using established methodologies defining diffusion. Analyses in diffusion using a small but reasonably sized vector-space with the GNMNTs will be exhaustively assessed and a comparison with the Rijndael cipher, the current advanced encryption standard (AES) algorithm, will be presented that will confirm strong diffusion characteristics. Implementation techniques using general-purpose computing on graphics processing units (GPGPU) have been applied, which are further assessed and discussed. Focus is drawn upon the future of cryptography and in particular cryptology, as a consequence of the emergence and rapid progress of GPGPU and consumer based parallel processing

Spectral modular arithmetic

In many areas of engineering and applied mathematics, spectral methods provide very powerful tools for solving and analyzing problems. For instance, large to extremely large sizes of numbers can efficiently be multiplied by using discrete Fourier transform and convolution property. Such computations are needed when computing π to millions of digits of precision, factoring and also big prime search projects. When it comes to the utilization of spectral techniques for modular operations in public key cryptosystems two difficulties arise; the first one is the reduction needed after the multiplication step and the second is the cryptographic sizes which are much shorter than the optimal asymptotic crossovers of spectral methods. In this dissertation, a new modular reduction technique is proposed. Moreover, modular multiplication is given based on this reduction. These methods work fully in the frequency domain with some exceptions such as the initial, final and partial transformations steps. Fortunately, the new technique addresses the reduction problem however, because of the extra complexity coming from the overhead of the forward and backward transformation computations, the second goal is not easily achieved when single operations such as modular multiplication or reduction are considered. On the contrary, if operations that need several modular multiplications with respect to the same modulus are considered, this goal is more tractable. An obvious example of such an operation is the modular exponentiation i.e., the computation of c=m[superscript e] mod n where c, m, e, n are large integers. Therefore following the spectral modular multiplication operation a new modular exponentiation method is presented. Since forward and backward transformation calculations do not need to be performed for every multiplication carried during the exponentiation, the asymptotic crossover for modular exponentiation is decreased to cryptographic sizes. The method yields an efficient and highly parallel architecture for hardware implementations of public-key cryptosystems

Design of tch-type sequences for communications

This thesis deals with the design of a class of cyclic codes inspired by TCH codewords. Since TCH codes are linked to finite fields the fundamental concepts and facts about abstract algebra, namely group theory and number theory, constitute the first part of the thesis. By exploring group geometric properties and identifying an equivalence between some operations on codes and the symmetries of the dihedral group we were able to simplify the generation of codewords thus saving on the necessary number of computations. Moreover, we also presented an algebraic method to obtain binary generalized TCH codewords of length N = 2k, k = 1,2, . . . , 16. By exploring Zech logarithm’s properties as well as a group theoretic isomorphism we developed a method that is both faster and less complex than what was proposed before. In addition, it is valid for all relevant cases relating the codeword length N and not only those resulting from N = p

UWB communication systems acquisition at symbol rate sampling for IEEE standard channel models

For ultra-wideband (UWB) communications, acquisition is challenging. The reason is from the ultra short pulse shape and ultra dense multipath interference. Ultra short pulse indicates the acquisition region is very narrow. Sampling is another challenge for UWB design due to the need for ultra high speed analog-to digital converter.A sub-optimum and under-sampling scheme using pilot codes as transmitted reference is proposed here for acquisition. The sampling rate for the receiver is at the symbol rate. A new architecture, the reference aided matched filter is studied in this project. The reference aided matched filter method avoids using complex rake receiver to estimate channel parameters and high sampling rate for interpolation. A limited number of matched filters are used as a filter bank to search for the strongest path. Timing offset for acquisition is then estimated and passed to an advanced verification algorithm. For optimum performance of acquisition, the adaptive post detection integration is proposed to solve the problem from dense inter-symbol interference during the acquisition. A low-complex early-late gate tracking loop is one element of the adaptive post detection integration. This tracking scheme assists in improving acquisition accuracy. The proposed scheme is evaluated using Matlab Simulink simulations in term of mean acquisition time, system performance and false alarm. Simulation results show proposed algorithm is very effective in ultra dense multipath channels. This research proves reference aided acquisition with tracking loop is promising in UWB application

Frequency Domain Finite Field Arithmetic for Elliptic Curve Cryptography

Efficient implementation of the number theoretic transform(NTT), also known as the discrete Fourier transform(DFT) over a finite field, has been studied actively for decades and found many applications in digital signal processing. In 1971 Schonhage and Strassen proposed an NTT based asymptotically fast multiplication method with the asymptotic complexity O(m log m log log m) for multiplication of $m$-bit integers or (m-1)st degree polynomials. Schonhage and Strassen\u27s algorithm was known to be the asymptotically fastest multiplication algorithm until Furer improved upon it in 2007. However, unfortunately, both algorithms bear significant overhead due to the conversions between the time and frequency domains which makes them impractical for small operands, e.g. less than 1000 bits in length as used in many applications. With this work we investigate for the first time the practical application of the NTT, which found applications in digital signal processing, to finite field multiplication with an emphasis on elliptic curve cryptography(ECC). We present efficient parameters for practical application of NTT based finite field multiplication to ECC which requires key and operand sizes as short as 160 bits in length. With this work, for the first time, the use of NTT based finite field arithmetic is proposed for ECC and shown to be efficient. We introduce an efficient algorithm, named DFT modular multiplication, for computing Montgomery products of polynomials in the frequency domain which facilitates efficient multiplication in GF(p^m). Our algorithm performs the entire modular multiplication, including modular reduction, in the frequency domain, and thus eliminates costly back and forth conversions between the frequency and time domains. We show that, especially in computationally constrained platforms, multiplication of finite field elements may be achieved more efficiently in the frequency domain than in the time domain for operand sizes relevant to ECC. This work presents the first hardware implementation of a frequency domain multiplier suitable for ECC and the first hardware implementation of ECC in the frequency domain. We introduce a novel area/time efficient ECC processor architecture which performs all finite field arithmetic operations in the frequency domain utilizing DFT modular multiplication over a class of Optimal Extension Fields(OEF). The proposed architecture achieves extension field modular multiplication in the frequency domain with only a linear number of base field GF(p) multiplications in addition to a quadratic number of simpler operations such as addition and bitwise rotation. With its low area and high speed, the proposed architecture is well suited for ECC in small device environments such as smart cards and wireless sensor networks nodes. Finally, we propose an adaptation of the Itoh-Tsujii algorithm to the frequency domain which can achieve efficient inversion in a class of OEFs relevant to ECC. This is the first time a frequency domain finite field inversion algorithm is proposed for ECC and we believe our algorithm will be well suited for efficient constrained hardware implementations of ECC in affine coordinates

Architectures and Algorithms for the Signal Processing of Advanced MIMO Radar Systems

This thesis focuses on the research, development and implementation of novel concepts, architectures, demonstrator systems and algorithms for the signal processing of advanced Multiple Input Multiple Output (MIMO) radar systems. The key concept is to address compact system, which have high resolutions and are able to perform a fast radar signal processing, three-dimensional (3D), and four-dimensional (4D) beamforming for radar image generation and target estimation. The idea is to obtain a complete sensing of range, Azimuth and elevation (additionally Doppler as the fourth dimension) from the targets in the radar captures. The radar technology investigated, aims at addressing sev- eral civil and military applications, such as surveillance and detection of targets, both air and ground based, and situational awareness, both in cars and in flying platforms, from helicopters, to Unmanned Aerial Vehicles (UAV) and air-taxis. Several major topics have been targeted. The development of complete systems and innovative FPGA, ARM and software based digital architectures for 3D imaging MIMO radars, which operate in both Time Division Multiplexing (TDM) and Frequency Divi- sion Multiplexing (FDM) modes, with Frequency Modulated Continuous Wave (FMCW) and Orthogonal Frequency Division Multiplexing (OFDM) signals, respectively. The de- velopment of real-time radar signal processing, beamforming and Direction-Of-Arrival (DOA) algorithms for target detection, with particular focus on FFT based, hardware implementable techniques. The study and implementation of advanced system concepts, parametrisation and simulation of next generation real-time digital radars (e.g. OFDM based). The design and development of novel constant envelope orthogonal waveforms for real-time 3D OFDM MIMO radar systems. The MIMO architectures presented in this thesis are a collection of system concepts, de- sign and simulations, as well as complete radar demonstrators systems, with indoor and outdoor measurements. Several of the results shown, come in the form of radar images which have been captured in field-test, in different scenarios, which aid in showing the proper functionality of the systems. The research activities for this thesis, have been carried out on the premises of Air- bus, based in Munich (Germany), as part of a Ph.D. candidate joint program between Airbus and the Polytechnic Department of Engineering and Architecture (Dipartimento Politecnico di Ingegneria e Architettura), of the University of Udine, based in Udine (Italy).Questa tesi si concentra sulla ricerca, lo sviluppo e l\u2019implementazione di nuovi concetti, architetture, sistemi dimostrativi e algoritmi per l\u2019elaborazione dei segnali in sistemi radar avanzati, basati su tecnologia Multiple Input Multiple Output (MIMO). Il con- cetto chiave `e quello di ottenere sistemi compatti, dalle elevate risoluzioni e in grado di eseguire un\u2019elaborazione del segnale radar veloce, un beam-forming tri-dimensionale (3D) e quadri-dimensionale (4D) per la generazione di immagini radar e la stima delle informazioni dei bersagli, detti target. L\u2019idea `e di ottenere una stima completa, che includa la distanza, l\u2019Azimuth e l\u2019elevazione (addizionalmente Doppler come quarta di- mensione) dai target nelle acquisizioni radar. La tecnologia radar indagata ha lo scopo di affrontare diverse applicazioni civili e militari, come la sorveglianza e la rilevazione di targets, sia a livello aereo che a terra, e la consapevolezza situazionale, sia nelle auto che nelle piattaforme di volo, dagli elicotteri, ai Unmanned Aerial Vehicels (UAV) e taxi volanti (air-taxis). Le tematiche affrontante sono molte. Lo sviluppo di sistemi completi e di architetture digitali innovative, basate su tecnologia FPGA, ARM e software, per radar 3D MIMO, che operano in modalit`a Multiplexing Time Division Multiplexing (TDM) e Multiplexing Frequency Diversion (FDM), con segnali di tipo FMCW (Frequency Modulated Contin- uous Wave) e Orthogonal Frequency Division Multiplexing (OFDM), rispettivamente. Lo sviluppo di tecniche di elaborazione del segnale radar in tempo reale, algoritmi di beam-forming e di stima della direzione di arrivo, Direction-Of-Arrival (DOA), dei seg- nali radar, per il rilevamento dei target, con particolare attenzione a processi basati su trasformate di Fourier (FFT). Lo studio e l\u2019implementazione di concetti di sistema avan- zati, parametrizzazione e simulazione di radar digitali di prossima generazione, capaci di operare in tempo reale (ad esempio basati su architetture OFDM). Progettazione e sviluppo di nuove forme d\u2019onda ortogonali ad inviluppo costante per sistemi radar 3D di tipo OFDM MIMO, operanti in tempo reale. Le attivit`a di ricerca di questa tesi sono state svolte presso la compagnia Airbus, con sede a Monaco di Baviera (Germania), nell\u2019ambito di un programma di dottorato, svoltosi in maniera congiunta tra Airbus ed il Dipartimento Politecnico di Ingegneria e Architettura dell\u2019Universit`a di Udine, con sede a Udine