BKM: a new hardware algorithm for complex elementary functions

A new algorithm for computing the complex logarithm and exponential functions is proposed. This algorithm is based on shift-and-add elementary steps, and it generalizes some algorithms by Briggs and De Lugish (1970), as well as the CORDIC algorithm. It can easily be used to compute the classical real elementary functions (sin, cos, arctan, ln, exp). This algorithm is more suitable for computations in a redundant number system than the CORDIC algorithm, since there is no scaling factor when computing trigonometric function

An approach to the application of shift-and-add algorithms on engineering and industrial processes

Different kinds of algorithms can be chosen so as to compute elementary functions. Among all of them, it is worthwhile mentioning the shift-and-add algorithms due to the fact that they have been specifically designed to be very simple and to save computer resources. In fact, almost the only operations usually involved with these methods are additions and shifts, which can be easily and efficiently performed by a digital processor. Shift-and-add algorithms allow fairly good precision with low cost iterations. The most famous algorithm belonging to this type is CORDIC. CORDIC has the capability of approximating a wide variety of functions with only the help of a slight change in their iterations. In this paper, we will analyze the requirements of some engineering and industrial problems in terms of type of operands and functions to approximate. Then, we will propose the application of shift-and-add algorithms based on CORDIC to these problems. We will make a comparison between the different methods applied in terms of the precision of the results and the number of iterations required.This research was supported by the Conselleria de Educacion of the Valencia Region Government under grant number GV/2011/043

Algorithms and architectures for decimal transcendental function computation

Nowadays, there are many commercial demands for decimal floating-point (DFP) arithmetic operations such as financial analysis, tax calculation, currency conversion, Internet based applications, and e-commerce. This trend gives rise to further development on DFP arithmetic units which can perform accurate computations with exact decimal operands. Due to the significance of DFP arithmetic, the IEEE 754-2008 standard for floating-point arithmetic includes it in its specifications. The basic decimal arithmetic unit, such as decimal adder, subtracter, multiplier, divider or square-root unit, as a main part of a decimal microprocessor, is attracting more and more researchers' attentions. Recently, the decimal-encoded formats and DFP arithmetic units have been implemented in IBM's system z900, POWER6, and z10 microprocessors. Increasing chip densities and transistor count provide more room for designers to add more essential functions on application domains into upcoming microprocessors. Decimal transcendental functions, such as DFP logarithm, antilogarithm, exponential, reciprocal and trigonometric, etc, as useful arithmetic operations in many areas of science and engineering, has been specified as the recommended arithmetic in the IEEE 754-2008 standard. Thus, virtually all the computing systems that are compliant with the IEEE 754-2008 standard could include a DFP mathematical library providing transcendental function computation. Based on the development of basic decimal arithmetic units, more complex DFP transcendental arithmetic will be the next building blocks in microprocessors. In this dissertation, we researched and developed several new decimal algorithms and architectures for the DFP transcendental function computation. These designs are composed of several different methods: 1) the decimal transcendental function computation based on the table-based first-order polynomial approximation method; 2) DFP logarithmic and antilogarithmic converters based on the decimal digit-recurrence algorithm with selection by rounding; 3) a decimal reciprocal unit using the efficient table look-up based on Newton-Raphson iterations; and 4) a first radix-100 division unit based on the non-restoring algorithm with pre-scaling method. Most decimal algorithms and architectures for the DFP transcendental function computation developed in this dissertation have been the first attempt to analyze and implement the DFP transcendental arithmetic in order to achieve faithful results of DFP operands, specified in IEEE 754-2008. To help researchers evaluate the hardware performance of DFP transcendental arithmetic units, the proposed architectures based on the different methods are modeled, verified and synthesized using FPGAs or with CMOS standard cells libraries in ASIC. Some of implementation results are compared with those of the binary radix-16 logarithmic and exponential converters; recent developed high performance decimal CORDIC based architecture; and Intel's DFP transcendental function computation software library. The comparison results show that the proposed architectures have significant speed-up in contrast to the above designs in terms of the latency. The algorithms and architectures developed in this dissertation provide a useful starting point for future hardware-oriented DFP transcendental function computation researches

Processing of DMSP magnetic data: Handbook of programs, tapes, and datasets

The DMSP F-7 satellite was an operational Air Force meteorological satellite which carried a magnetometer for geophysical measurements. The magnetometer was located within the body of the spacecraft in the presence of large spacecraft fields. In addition to stray magnetic fields, the data have inherent position and time inaccuracies. Algorithms were developed to identify and remove time varying magnetic field noise from the data. These algorithms are embodied in an automated procedure which fits a smooth curve through the data and then identifies outliers and which filters the predominant Fourier component of noise from the data. Techniques developed for Magsat were then modified and used to attempt determination of the spacecraft fields, of any rotation between the magnetometer axes and the spacecraft axes, and of any scale changes within the magnetometer itself. Software setup and usage are documented and program listings are included in the Appendix. The initial and resulting data are archived on magnetic cartridge and the formats are documented

Система обчислення функцій на ПЛІС в онлайн режимі

Дана робота присвячена розробці пристрою для обчислення функцій у режимі онлайн, що реалізується на ПЛІС. Так як у даний момент індустрія ПЛІС активно розвивається, разом із тим зростає потреба їх застосування у різних галузях науки і техніки. Однак з розвитком обчислювальної здатності ПЛІС, кількість елементів взаємодії (елементів введення-виведення, піни) збільшується набагато повільніше, адже це напряму залежить від розміру схеми і також зростає можливість сповільнення роботи, або взагалі відмови системи, через надмірне споживання внутрішніх зв’язків. Запропонований обчислювач використовує метод порозрядного введення операндів у надлишковій системі, суміщене з ним виконання операцій та таке ж порозрядне виведення результату. Це призводить до скорочення необхідного часу обробки, кількості пінів та з’являється можливість динамічно керувати точністю результатів. Пристрій створений на основі рекурсивно-цифрового фільтру за допомогою мови опису апаратури VHDL та САПР Active-HDL. Синтез здійснювався з використанням САПР Quartus II на ПЛІС від компанії Altera: Cyclone III EP3C5E144A7.This work is devoted to the development of a device for calculating functions in online mode, which is implemented on FPGA. As the FPGA industry is currently actively developing, the need for their application in various fields of science and technology is growing. However, with the development of FPGA computing power, the number of interaction elements (I / O elements, pins) increases much more slowly, as it directly depends on the size of the circuit and also increases the possibility of slowing down or system failure, due to excessive consumption of internal connections. The proposed calculation system uses the method of bitwise input of operands in the redundant system, dependent operations overlapping and the same bitwise output of the result. This reduces the processing time; the number of pins and it is possible to dynamically control the accuracy of the results. The device is based on a recursive digital filter using the VHDL description language and Active-HDL. The synthesis was performed using Quartus II on FPGA from Altera: Cyclone III EP3C5E144A7

Portable Ultrasound Imaging

This PhD project investigates hardware strategies and imaging methods for hand-held ultrasound systems. The overall idea is to use a wireless ultrasound probe linked to general-purpose mobile devices for the processing and visualization. The approach has the potential to reduce the upfront costs of the ultrasound system and, consequently, to allow for a wide-scale utilization of diagnostic ultrasound in any medical specialties and out of the radiology department. The first part of the contribution deals with the study of hardware solutions for the reduction of the system complexity. Analog and digital beamforming strategies are simulated from a system-level perspective. The quality of the B-mode image is evaluated and the minimum specifications are derived for the design of a portable probe with integrated electronics in-handle. The system is based on a synthetic aperture sequential beamforming approach that allows to significantly reduce the data rate between the probe and processing unit. The second part investigates the feasibility of vector flow imaging in a hand-held ultrasound system. Vector flow imaging overcomes the limitations of conventional imaging methods in terms of flow angle compensation. Furthermore, high frame rate can be obtained by using synthetic aperture focusing techniques. A method is developed combining synthetic aperture sequential beamforming and directional transverse oscillation to achieve the wireless transmission of the data along with a relatively inexpensive 2-D velocity estimation. The performance of the method is thoroughly assessed through simulations and measurements, and in vivo investigations are carried out to show its potential in presence of complex flow dynamics. A sufficient frame rate is achieved to allow for the visualization of vortices in the carotid bifurcation. Furthermore, the method is implemented on a commercially available tablet to evaluate the real-time processing performance in the built-in GPU with concurrent wireless transmission of the data. Based on the demonstrations in this thesis, a flexible framework can be implemented with performance that can be scaled to the needs of the user and according to the computing resources available. The integration of high-frame-rate vector flow imaging in a hand-held ultrasound scanner, in addition, has the potential to improve the operator’s workflow and opens the way to new possibilities in the clinical practice

Topic extraction for ontology learning

This chapter addresses the issue of topic extraction from text corpora for ontology learning. The first part provides an overview of some of the most significant solutions present today in the literature. These solutions deal mainly with the inferior layers of the Ontology Learning Layer Cake. They are related to the challenges of the Terms and Synonyms layers. The second part shows how these pieces can be bound together into an integrated system for extracting meaningful topics. While the extracted topics are not proper concepts as yet, they constitute a convincing approach towards concept building and therefore ontology learning. This chapter concludes by discussing the research undertaken for filling the gap between topics and concepts as well as perspectives that emerge today in the area of topic extraction. © 2011, IGI Global

MaxSAT Evaluation 2019 : Solver and Benchmark Descriptions

Non peer reviewe