Resistive Solid State Protective Device

Abstract: This thesis describes and explains different fault to characterize fault specifically for DC distribution systems and DC Microgrids fed by synchronous generators. This will result in a testbed for static and intermittent line-to-line faults, and in future work, various types of ground faults. Automaton allows for repeated testing at various voltage levels and precise control over intermittent fault generation. The fault generator is implemented with an IGBT H-bridge topology. Its physical implementation and benefits are described. Experimental results are shown for static line-to-line fault. This testbed will be used to help develop closed-form expressions. Once fault currents are characterized and closed-form expressions are made, adequate protection systems can be designed. finally, this paper will include the simulation and experimental results of line-to-line fault characterization with a DC smoothing capacitor, and intermittent faults of various times

Uranium Dioxide Actinide Detection Device Support Design for Space Applications

Attention concerning the proliferation of nuclear weapons and materials has generated many research initiatives to detect, identify, and locate radiation emitted by actinides. In support of this effort, the `Fission Induced Neutron Detection of Nuclear Materials\u27 (FIND\u27NM) program was established to comprise a joint effort to explore this issue. The objective also co-extends the Air Force Research Laboratory uranium dioxide (UO2) detection sample growth, characterization, and electrical interface research. AFIT\u27s study accomplishes the design and fabrication of a space-tolerant PCB to support a UO2-based neutron detector. Further design considerations are made with the expectation of the platform to be inside an in-orbit satellite. The PCB will interface a satellite, which in turn will relay transferred data to researchers on the ground for later processing. The scope of the research is to provide a low-cost commercial-off-the-shelf solution with signal integrity and operational stability in mind. The study performed by LTC Dugan [16] and Lt Col Young [44] provided the basis from which the project stems. These circuit behavioral characteristics narrowed the components considered to accommodate the low-amplitude and fast-pulse output required from a device. Three distinct amplifier designs were required due to changes in the accepted theoretical electrical characteristics of the sensor. By circuit simulation, the three presented amplifier systems demonstrate the desired output for each sensor model, within a particular envelope of operation. The system can capture, collate, and disseminate data generated while operating within specified parameters. The completed and operational PCB presents a proof-of-concept that Space compliance devices can be made more cost-efficient by utilizing design aspects already included in larger system designs. The flexibility of the FPGA signal processing system can be used to try multiple operating configurations, ultimately resulting in an ASIC to further reduce the cost given large scale deployment of a unique design. Small detection devices like this could be installed on most orbital satellites and transmit data about areas of interest where actinide particle activity is detected

Development of an electronic control unit for the T63 gas turbine

Includes bibliographical references.Fundamental research has been undertaken at the SASOL Advanced Fuels Laboratory to investigate the effects of the chemistry and physical properties of both conventional and synthetic jet fuels on threshold combustion. This research was undertaken using a purpose built low pressure continuous combustion test facility. Researchers at the laboratory now wish to examine these effects on an aviation gas turbine in service for which “off-map” scheduling of fuel to the engine would be required. A two phase project was thus proposed to develop this capability; the work of this thesis embodies Phase I of that project

A Hardware-in-the-Loop Platform for DC Protection

With the proliferation of power electronics, dc-based power distribution systems can be realized; however, dc electrical protection remains a significant barrier to mass implementation dc power distribution. Controller Hardware-in-the-loop (CHiL) simulation enables moving up technology readiness levels (TRL) quickly. This work presents an end-to-end solution for dc protection CHiL for early design exploration and verification for dc protection, allowing for the rapid development of dc protection schemes for both Line-to-Line (LL) and Line-to-Ground (LG) faults. The approach combines using Latency Based Linear Multistep Compound (LB-LMC), a real-time simulation method for power electronic, and National Instruments (NI) FPGA hardware to enable dc protection design with CHiL. A case study is performed for a 1.5 MW Voltage Source Rectifier (VSR) under LL and LG faults in an ungrounded system. The deficiency in real-time simulation resolution of Commercial-off-the-Shelf (COTS) for dc fault transients is shown, and addressed by using LB-LMC RT solver inside NI FPGA hardware to achieve 50 ns resolution of dc fault transients

Investigation on the Benefits of Safety Margin Improvement in CANDU Nuclear Power Plant Using an FPGA-based Shutdown System

The relationship between response time and safety margin of CANadian Deuterium Uranium (CANDU) nuclear power plant (NPP) is investigated in this thesis. Implementation of safety shutdown system using Field Programmable Gate Array (FPGA) is explored. The fast data processing capability of FPGAs shortens the response time of CANDU shutdown systems (SDS) such that the impact of accident transient can be reduced. The safety margin, which is closely related to the reactor behavior in the event of an accident, is improved as a result of such a faster shutdown process. Theoretical analysis based on neutron dynamic theory is carried out to establish the fact that a faster shutdown process can mitigate accidental consequences. To provide more realistic test cases from a thermalhydraulic perspective, an industry grade simulation tool known as CATHENA is used to generate comparable accident-shutdown transients for different SDS response times. Results from both verification methods explicitly prove the feasibility of improving the safety margin via faster shutdown process. To demonstrate this concept, a prototype of the proposed faster SDS is constructed. The trip logic of CANDU shutdown system No.1 (SDS1) is converted into a digital hardware design and implemented within chosen FPGA platform. The functionality of the FPGA-based SDS1 is implemented, and the response times are tested and compared to those of the existing CANDU SDS1. The achieved 10.5 ms response time of the FPGA-based SDS1 is again applied to the CATHENA simulation process to quantitatively present the 26.98% improvement in the safety margin. To investigate potential improvement in safety margin by using FPGA technology, hardware-in-the-loop (HIL) simulation is performed by connecting the FPGA-based SDS1 to an NPP training simulator. The 6.26% improvement in safety margin has been verified, based on which a 10% potential power upgrade is discussed as another benefit of applying FPGA technology to CANDU NPPs

Novel Pilot Directional Protection for the FREEDM Smart Grid System

abstract: The presence of distributed generation in high renewable energy penetration system increases the complexity for fault detection as the power flow is bidirectional. The conventional protection scheme is not sufficient for the bidirectional power flow system, hence a fast and accurate protection scheme needs to be developed. This thesis mainly deals with the design and validation of the protection system based on the Future Renewable Electric Energy Delivery and Management (FREEDM) system, which is a bidirectional power flow loop system. The Large-Scale System Simulation (LSSS) is a system level PSCAD model which is used to validate component models for different time-scale platforms to provide a virtual testing platform for the Future Renewable Electric Energy Delivery and Management (FREEDM) system. It is also used to validate the cases of power system protection, renewable energy integration and storage, and load profiles. The protection of the FREEDM system against any abnormal condition is one of the important tasks. Therefore, the pilot directional protection scheme based on wireless communication is used in this thesis. The use of wireless communication is extended to protect the large scale meshed distributed generation from any fault. The complete protection system consists of the main protection and the back-up protection which are both presented in the thesis. The validation of the protection system is performed on a radial system test bed using commercial relays at the ASU power laboratory, and on the RTDS platform (Real Time Digital Power System) in CAPS (Center for Advanced Power System) Florida. Considering that the commercial relays have limitations of high cost and communicating with fault isolation devices, a hardware prototype using the interface between the ADC (analog to digital converter) and MATLAB software is developed, which takes advantage of economic efficiency and communication compatibility. Part of this research work has been written into a conference paper which was presented by IEEE Green Tech Meeting, 2017.Dissertation/ThesisMasters Thesis Electrical Engineering 201

SCA security verification on wireless sensor network node

Side Channel Attack (SCA) differs from traditional mathematic attacks. It gets around of the exhaustive mathematic calculation and precisely pin to certain points in the cryptographic algorithm to reveal confidential information from the running crypto-devices. Since the introduction of SCA by Paul Kocher et al [1], it has been considered to be one of the most critical threats to the resource restricted but security demanding applications, such as wireless sensor networks. In this paper, we focus our work on the SCA-concerned security verification on WSN (wireless sensor network). A detailed setup of the platform and an analysis of the results of DPA (power attack) and EMA (electromagnetic attack) is presented. The setup follows the way of low-cost setup to make effective SCAs. Meanwhile, surveying the weaknesses of WSNs in resisting SCA attacks, especially for the EM attack. Finally, SCA-Prevention suggestions based on Differential Security Strategy for the FPGA hardware implementation in WSN will be given, helping to get an improved compromise between security and cost

High speed digital protection of EHV transmission lines using traveling waves

Extra High Voltage (EHV) transmission lines are designed to transfer large amount of power from one location to another. The length exposed to the environment is a major reason for occurrence of faults on the lines. A fault on a high voltage transmission line affects the stability of the overall power system, which sometimes leads to permanent damage of the equipment. Relays are developed and installed to protect the lines. The transmission line protection relays, in the industry, are based on the fundamental frequency components of the voltages and currents. These relays need at least one fundamental frequency cycle for performing the protection operation. Voltage and current traveling waves are generated when a fault occurs on the transmission line. The velocity of propagation of traveling waves is finite and the level of the waves decreases with increase in the distance traveled. Information about the fault can be obtained by analyzing the traveling waves. A few traveling wave techniques, which are based on analog signal processing, to protect transmission lines have been proposed in the past. Two digital techniques, which use traveling waves for protecting EHV transmission lines, are proposed in this thesis. The traveling waves are extracted from the modal voltages and currents at the terminals of the transmission line. The techniques identify and locate the fault by using the information contained in the waves. A power system was modeled in the Electromagnetic Transient Direct Current Analysis (EMTDC) and several cases were created by varying different parameters related to the fault, fault type, fault location, fault resistance and fault inception angle. The techniques were implemented in hardware and their performance was tested on data, generated from the EMTDC simulations. Some cases are discussed in the thesis. The performance of the digital techniques for protecting EHV transmission lines using traveling waves was confirmed to be satisfactory. The proposed techniques provide protection at speed and discriminate well between internal and external faults

A Fixed-Latency Architecture to Secure GOOSE and Sampled Value Messages in Substation Systems

International Electrotechnical Commission (IEC) 62351-6 standard specifies the security mechanisms to protect real-time communications based on IEC 61850. Generic Object Oriented Substation Events (GOOSE) and Sampled Value (SV) messages must be generated, transmitted and processed in less than 3 ms, which challenges the introduction of IEC 62351-6. After evaluating the security threats to IEC 61850 communications and the state of the art in GOOSE and SV security, this work presents a novel architecture based on wire-speed processing able to provide message authentication and confidentiality. This architecture has been implemented and tested to evaluate its performance, resource usage, and the latency introduced. Other proposals in the scientific literature do not support real-time traffic, so they are not suitable for GOOSE and SV messages. Whereas the others exceed the target latency of 3 ms or do not comply with the standards, our design authenticates and encrypts real-time IEC 61850 data in less than 7 mu s-predictable latency-, and complies with IEC 62351:2020.This work was supported in part by the Ministerio de Economia y Competitividad of Spain under Project TEC2017-84011-R, in part by Fondo Europeo de Desarrollo Regional (FEDER) Funds through the Doctorados Industriales program under Grant DI-15-07857, and in part by the Department of Education, Linguistic Policy and Culture of the Basque Government through the Fund for Research Groups of the Basque University System under Grant IT978-16