High Performance FPGA-oriented mersenne twister uniform random number generator

Mersenne Twister (MT) uniform random number generators are key cores for hardware acceleration of Monte Carlo simulations. In this work, two different architectures are studied: besides the classical table-based architecture, a different architecture based on a circular buffer and especially targeting FPGAs is proposed. A 30% performance improvement has been obtained when compared to the fastest previous work. The applicability of the proposed MT architectures has been proven in a high performance Gaussian RNG

A new channel selection algorithm for the Weightless-N Frequency Hopping with lower collision probability

There are different techniques used by Machine-to-machine (M2M) communications technologies to mitigate collision problem and data loss. One of these techniques is Frequency Hopping (FH), which is used by Weightless-N technology with a special random channel selection algorithm. In such a system, the probability of a message collision mainly depends on the randomisation algorithm used to access channels. This paper provides a novel randomisation algorithm for the channel selection process of the Weightless-N system. The new proposed algorithm is based on a uniform randomisation distribution and called a Uniform Randomisation Channel Selection Technique (URCST). This new algorithm provides a better system performance and lower probability of collision. In addition, it is faster and easier than the Mersenne Twister algorithm

Pre-silicon FEC decoding verification on SoC FPGAs

Forward error correction (FEC) decoding hardware modules are challenging to verify at pre-silicon stage, when they are usually described at register-transfer (RT)/logic level with a hardware description language (HDL). They tend to hide faults due to their inherent tendency to correct errors and the required simulations with a massive insertion of inputs are too slow. In this work, two verification techniques based on FPGA-prototyping are applied in order to complement the mentioned simulations: golden model vs implementation matching with thousands of random codewords and codeword/bit error rate (CER/BER) curve computation. For this purpose, a system on chip (SoC) field-programmable gate array (FPGA) is used, implementing in the programmable hardware part several replicas of the decoder (exploiting the parallel capabilities of hardware) and managing the verification by parallel programming the software part of the SoC (exploiting the presence of multiple processing cores). The presented approach allows a seamless integration with high-level models, does not need expensive testing/emulation platforms and obtains the results in a reasonable amount of time.This work has been supported by Project TEC2017-86722-C4-3-R, funded by Spanish MICINN/AEI

Signal design and processing for noise radar

An efficient and secure use of the electromagnetic spectrum by different telecommunications and radar systems represents, today, a focal research point, as the coexistence of different radio-frequency sources at the same time and in the same frequency band requires the solution of a non-trivial interference problem. Normally, this is addressed with diversity in frequency, space, time, polarization, or code. In some radar applications, a secure use of the spectrum calls for the design of a set of transmitted waveforms highly resilient to interception and exploitation, i.e., with low probability of intercept/ exploitation capability. In this frame, the noise radar technology (NRT) transmits noise-like waveforms and uses correlation processing of radar echoes for their optimal reception. After a review of the NRT as developed in the last decades, the aim of this paper is to show that NRT can represent a valid solution to the aforesaid problems

Proceedings of the First International Workshop on HyperTransport Research and Applications (WHTRA2009)

Proceedings of the First International Workshop on HyperTransport Research and Applications (WHTRA2009) which was held Feb. 12th 2009 in Mannheim, Germany. The 1st International Workshop for Research on HyperTransport is an international high quality forum for scientists, researches and developers working in the area of HyperTransport. This includes not only developments and research in HyperTransport itself, but also work which is based on or enabled by HyperTransport. HyperTransport (HT) is an interconnection technology which is typically used as system interconnect in modern computer systems, connecting the CPUs among each other and with the I/O bridges. Primarily designed as interconnect between high performance CPUs it provides an extremely low latency, high bandwidth and excellent scalability. The definition of the HTX connector allows the use of HT even for add-in cards. In opposition to other peripheral interconnect technologies like PCI-Express no protocol conversion or intermediate bridging is necessary. HT is a direct connection between device and CPU with minimal latency. Another advantage is the possibility of cache coherent devices. Because of these properties HT is of high interest for high performance I/O like networking and storage, but also for co-processing and acceleration based on ASIC or FPGA technologies. In particular acceleration sees a resurgence of interest today. One reason is the possibility to reduce power consumption by the use of accelerators. In the area of parallel computing the low latency communication allows for fine grain communication schemes and is perfectly suited for scalable systems. Summing up, HT technology offers key advantages and great performance to any research aspect related to or based on interconnects. For more information please consult the workshop website (http://whtra.uni-hd.de)