Digitally-Assisted RF IC Design Techniques for Reliable Performance

Semiconductor industries have competitively scaled down CMOS devices to attain benefits of low cost, high performance, and high integration density in digital integrated circuits. On the other hand, deep scaled technologies inextricably accompany a large process variation, supply voltage scaling, and reduction in breakdown voltages of transistors. When it comes to RF/analog IC design, CMOS scaling adversely affects its reliability due to large performance variation and limited linearity. For addressing the issues related to variations and linearity, this research proposes the following digitally-assisted RF circuit design techniques: self-calibration system for RF phase shifters and wide dynamic range LNAs. Due to PVT variations in scaled technologies, RF phase shifter design becomes more challenging with device scaling. In the proposed self-calibration topology, we devised a novel phase sensing method and a pulsewidth-to-digital converter. The feedback controller is also designed in digital domain, which is robust to PVT variations. These unique techniques enable a sensing/control loop tolerant to PVT variations. The self-calibration loop was applied to a 7 to 13GHz phase shifter. With the calibration, the estimated phase error is less than 2 degrees. To overcome the linearity issue in scaled technologies, a digitally-controlled dual-mode LNA design is presented. A narrowband (5.1GHz) and a wideband (0.8 to 6GHz) LNA can be toggled between high-gain and high-linearity modes by digital control bits according to the input signal power. A compact design, which provides negligible performance degradation by additional circuitry, is achieved by sharing most of the components between the two operation modes. The narrowband and the wideband LNA achieves an input-referred P1dB of -1.8dBm and +4.2dBm, respectively

Investigation of LSTM Based Prediction for Dynamic Energy Management in Chip Multiprocessors

In this paper, we investigate the effectiveness of using long short-term memory (LSTM) instead of Kalman filtering to do prediction for the purpose of constructing dynamic energy management (DEM) algorithms in chip multi-processors (CMPs). Either of the two prediction methods is employed to estimate the workload in the next control period for each of the processor cores. These estimates are then used to select voltage-frequency (VF) pairs for each core of the CMP during the next control period as part of a dynamic voltage and frequency scaling (DVFS) technique. The objective of the DVFS technique is to reduce energy consumption under performance constraints that are set by the user. We conduct our investigation using a custom Sniper system simulation framework. Simulation results for 16 and 64 core network-on-chip based CMP architectures and using several benchmarks demonstrate that the LSTM is slightly better than Kalman filtering

An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration

We empirically evaluate an undervolting technique, i.e., underscaling the circuit supply voltage below the nominal level, to improve the power-efficiency of Convolutional Neural Network (CNN) accelerators mapped to Field Programmable Gate Arrays (FPGAs). Undervolting below a safe voltage level can lead to timing faults due to excessive circuit latency increase. We evaluate the reliability-power trade-off for such accelerators. Specifically, we experimentally study the reduced-voltage operation of multiple components of real FPGAs, characterize the corresponding reliability behavior of CNN accelerators, propose techniques to minimize the drawbacks of reduced-voltage operation, and combine undervolting with architectural CNN optimization techniques, i.e., quantization and pruning. We investigate the effect of environmental temperature on the reliability-power trade-off of such accelerators. We perform experiments on three identical samples of modern Xilinx ZCU102 FPGA platforms with five state-of-the-art image classification CNN benchmarks. This approach allows us to study the effects of our undervolting technique for both software and hardware variability. We achieve more than 3X power-efficiency (GOPs/W) gain via undervolting. 2.6X of this gain is the result of eliminating the voltage guardband region, i.e., the safe voltage region below the nominal level that is set by FPGA vendor to ensure correct functionality in worst-case environmental and circuit conditions. 43% of the power-efficiency gain is due to further undervolting below the guardband, which comes at the cost of accuracy loss in the CNN accelerator. We evaluate an effective frequency underscaling technique that prevents this accuracy loss, and find that it reduces the power-efficiency gain from 43% to 25%.Comment: To appear at the DSN 2020 conferenc