CAutoCSD-evolutionary search and optimisation enabled computer automated control system design

This paper attempts to set a unified scene for various linear time-invariant (LTI) control system design schemes, by transforming the existing concept of 'Computer-Aided Control System Design' (CACSD) to the novel 'Computer-Automated Control System Design' (CAutoCSD). The first step towards this goal is to accommodate, under practical constraints, various design objectives that are desirable in both time and frequency-domains. Such performance-prioritised unification is aimed to relieve practising engineers from having to select a particular control scheme and from sacrificing certain performance goals resulting from pre-committing to the adopted scheme. With the recent progress in evolutionary computing based extra-numeric, multi-criterion search and optimisation techniques, such unification of LTI control schemes becomes feasible, analytically and practically, and the resultant designs can be creative. The techniques developed are applied to, and illustrated by, three design problems. The unified approach automatically provides an integrator for zero-steady state error in velocity control of a DC motor, meets multiple objectives in designing an LTI controller for a non-minimum phase plant and offers a high-performing LTI controller network for a nonlinear chemical process

Optimal control of discrete-time switched linear systems via continuous parameterization

The paper presents a novel method for designing an optimal controller for discrete-time switched linear systems. The problem is formulated as one of computing the discrete mode sequence and the continuous input sequence that jointly minimize a quadratic performance index. State-of-art methods for solving such a control problem suffer in general from a high computational requirement due to the fact that an exponential number of switching sequences must be explored. The method of this paper addresses the challenge of the switching law design by introducing auxiliary continuous input variables and then solving a non-smooth block-sparsity inducing optimization problem.Comment: 6 pages, 2 figures, 2 tables; To appear in the Proceedings of IFAC World Congress, 201

Using Warp to Control Network Contention in Mermera

Parallel computing on a network of workstations can saturate the communication network, leading to excessive message delays and consequently poor application performance. We examine empirically the consequences of integrating a flow control protocol, called Warp control [Par93], into Mermera, a software shared memory system that supports parallel computing on distributed systems [HS93]. For an asynchronous iterative program that solves a system of linear equations, our measurements show that Warp succeeds in stabilizing the network's behavior even under high levels of contention. As a result, the application achieves a higher effective communication throughput, and a reduced completion time. In some cases, however, Warp control does not achieve the performance attainable by fixed size buffering when using a statically optimal buffer size. Our use of Warp to regulate the allocation of network bandwidth emphasizes the possibility for integrating it with the allocation of other resources, such as CPU cycles and disk bandwidth, so as to optimize overall system throughput, and enable fully-shared execution of parallel programs.NSF (IRI-8910195, IRI-9041581, CDA-8920936, CCR-9204284

Custom optimization algorithms for efficient hardware implementation

The focus is on real-time optimal decision making with application in advanced control systems. These computationally intensive schemes, which involve the repeated solution of (convex) optimization problems within a sampling interval, require more efficient computational methods than currently available for extending their application to highly dynamical systems and setups with resource-constrained embedded computing platforms. A range of techniques are proposed to exploit synergies between digital hardware, numerical analysis and algorithm design. These techniques build on top of parameterisable hardware code generation tools that generate VHDL code describing custom computing architectures for interior-point methods and a range of first-order constrained optimization methods. Since memory limitations are often important in embedded implementations we develop a custom storage scheme for KKT matrices arising in interior-point methods for control, which reduces memory requirements significantly and prevents I/O bandwidth limitations from affecting the performance in our implementations. To take advantage of the trend towards parallel computing architectures and to exploit the special characteristics of our custom architectures we propose several high-level parallel optimal control schemes that can reduce computation time. A novel optimization formulation was devised for reducing the computational effort in solving certain problems independent of the computing platform used. In order to be able to solve optimization problems in fixed-point arithmetic, which is significantly more resource-efficient than floating-point, tailored linear algebra algorithms were developed for solving the linear systems that form the computational bottleneck in many optimization methods. These methods come with guarantees for reliable operation. We also provide finite-precision error analysis for fixed-point implementations of first-order methods that can be used to minimize the use of resources while meeting accuracy specifications. The suggested techniques are demonstrated on several practical examples, including a hardware-in-the-loop setup for optimization-based control of a large airliner.Open Acces

A quantum dot-based frequency multiplier

Silicon offers the enticing opportunity to integrate hybrid quantum-classical computing systems on a single platform. For qubit control and readout, high-frequency signals are required. Therefore, devices that can facilitate its generation are needed. Here, we present a quantum dot-based radiofrequency multiplier operated at cryogenic temperatures. The device is based on the non-linear capacitance-voltage characteristics of quantum dot systems arising from their low-dimensional density of states. We implement the multiplier in a multi-gate silicon nanowire transistor using two complementary device configurations: a single quantum dot coupled to a charge reservoir and a coupled double quantum dot. We study the harmonic voltage conversion as a function of energy detuning, multiplication factor and harmonic phase noise and find near ideal performance up to a multiplication factor of 10. Our results demonstrate a method for high-frequency conversion that could be readily integrated into silicon-based quantum computing systems and be applied to other semiconductors.Comment: 17 pages, 16 figure