Interpretation and Regulation of Electronic Defects in IGZO TFTs Through Materials & Processes

The recent rise in the market for consumer electronics has fueled extensive research in the field of display. Thin-Film Transistors (TFTs) are used as active matrix switching devices for flat panel displays such as LCD and OLED. The following investigation involves an amorphous metal-oxide semiconductor that has the potential for improved performance over current technology, while maintaining high manufacturability. Indium-Gallium-Zinc-Oxide (IGZO) is a semiconductor material which is at the onset of commercialization. The low-temperature large-area deposition compatibility of IGZO makes it an attractive technology from a manufacturing standpoint, with an electron mobility that is 10 times higher than current amorphous silicon technology. The stability of IGZO TFTs continues to be a challenge due to the presence of defect states and problems associated with interface passivation. The goal of this dissertation is to further the understanding of the role of defect states in IGZO, and investigate materials and processes needed to regulate defects to the level at which the associated influence on device operation is controlled. The relationships between processes associated with IGZO TFT operation including IGZO sputter deposition, annealing conditions and back-channel passivation are established through process experimentation, materials analysis, electrical characterization, and modeling of electronic properties and transistor behavior. Each of these components has been essential in formulating and testing several hypotheses on the mechanisms involved, and directing efforts towards achieving the goal. Key accomplishments and quantified results are summarized as follows: • XPS analysis identified differences in oxygen vacancies in samples before and after oxidizing ambient annealing at 400 °C, showing a drop in relative integrated area of the O 1s peak from 32% to 19%, which experimentally translates to over a thousand fold decrease in the channel free electron concentration. • Transport behavior at cryogenic temperatures identified variable range hopping as the electron transport mechanism at temperature below 130 K, whereas at temperature greater than 130 K, the current vs temperature response followed an Arrhenius relationship consistent with extended state transport. • Refinement of an IGZO material model for TCAD simulation, which consists of oxygen vacancy donors providing an integrated space charge concentration NVO = +5e15 cm-3, and acceptor-like band-tail states with a total integrated ionized concentration of NTA = -2e18 cm-3. An intrinsic electron mobility was established to be Un = 12.7 cm2/V∙s. • A SPICE-compatible 2D on-state operation model for IGZO TFTs has been developed which includes the integration of drain-impressed deionization of band-tail states and results in a 2D modification of free channel charge. The model provides an exceptional match to measured data and TCAD simulation, with model parameters for channel mobility (Uch = 12 cm2/V∙s) and threshold voltage (VT = 0.14 V) having a close match to TCAD analogs. • TCAD material and device models for bottom-gate and double-gate TFT configurations have been developed which depict the role of defect states on device operation, as well as provide insight and support of a presented hypothesis on DIBL like device behavior associated with back-channel interface trap inhomogeneity. This phenomenon has been named Trap Associated Barrier Lowering (TABL). • A process integration scheme has been developed that includes IGZO back-channel passivation with PECVD SiO2, furnace annealing in O2 at 400 °C, and a thin capping layer of alumina deposited via atomic layer deposition. This process supports device stability when subjected to negative and positive bias stress conditions, and thermal stability up to 140 °C. It also enables TFT operation at short channel lengths (Leff ~ 3 µm) with steep subthreshold characteristics (SS ~ 120 mV/dec). The details of these contributions in the interpretation and regulation of electronic defect states in IGZO TFTs is presented, along with the support of device characteristics that are among the best reported in the literature. Additional material on a complementary technology which utilizes flash-lamp annealing of amorphous silicon will also be described. Flash-Lamp Annealed Polycrystalline Silicon (FLAPS) has realized n-channel and p-channel TFTs with promising results, and may provide an option for future applications with the highest performance demands. IGZO is rapidly emerging as the candidate to replace a-Si:H and address the performance needs of display products produced by large panel manufacturing

Analysis of amorphous indium-gallium-zinc-oxide thin-film transistor contact metal using Pilling-Bedworth theory and a variable capacitance diode model

It is widely reported that threshold voltage and on-state current of amorphous indium-gallium-zinc-oxide bottom-gate thin-film transistors are strongly influenced by the choice of source/drain contact metal. Electrical characterisation of thin-film transistors indicates that the electrical properties depend on the type and thickness of the metal(s) used. Electron transport mechanisms and possibilities for control of the defect state density are discussed. Pilling-Bedworth theory for metal oxidation explains the interaction between contact metal and amorphous indium-gallium-zinc-oxide, which leads to significant trap formation. Charge trapping within these states leads to variable capacitance diode-like behavior and is shown to explain the thin-film transistor operation.This work was supported by the Engineering and Physical Sciences Research CouncilThis is the author's accepted manuscript of the publication: http://dx.doi.org/10.1063/1.480199

Oxide transistors produced by Combustion Synthesis: Influence of the PVP on the properties of the insulator

Solution processing of amorphous metal oxides has been used as an option to implement in flexible electronics, allowing to reduce the associated costs, when compared with vacuum processes. Recent research has been more focused on the semiconductor layer; however, the dielectric layer is equally important since its responsible for the stability and electric performance of the device. This work aims to evaluate hybrid dielectric thin films, using aluminium oxide and different types of polyvinylpyrrolidone (PVP), both obtained by solution process using solution combustion synthesis (SCS), to study the influence of the amount of organic material used in the insulator layer, as well as to study the influence of the hybrid insulator obtained in oxide thin film transistors (TFTs) using indium-gallium-zinc-oxide (IGZO) and zinc-tin-oxide (ZTO) as semiconductor layer. The insulator layer was obtained using aluminium nitrate nonahydrate and polyvinylpyrrolidone (PVP) with different molecular weights (10000 and 40000) and different percentages as precursor solutions, using urea as fuel and 2-methoxyethanol as solvent. The best hybrid dielectric was obtained with 0.8 % PVP 40000 (weight per volume), showing a breakdown voltage of 1.1 MV/cm, low density leakage current of 9.6 × 10-5 A/cm2, capacitance per area of 123 nF/cm2, thickness of 49.35 nm, annealed at 200 °C for 30 minutes. Moreover, the roughness study obtained using atomic force microscopy showed highly smooth surface, resulting in improvement dielectric-semiconductor interface, while still maintaining an amorphous nature. These characteristics allowed this hybrid dielectric, lead to enhanced TFTs electrical properties. The best performing thin films were applied in IGZO TFTs as hybrid dielectrics. The optimized TFTs show good reproducibility with an average mobility of 40.24 ± 1.1 cm2∙V-1∙s-1, subthreshold slope of 0.169 ± 0.012 V∙dec-1, a turn-on voltage of 0.078 ± 0.004 V and a low operating voltage (maximum 2 V)

Ta2O5/SiO2 Multicomponent Dielectrics for Amorphous Oxide TFTs

Co-sputtering of SiO2 and high-κ Ta2O5 was used to make multicomponent gate dielectric stacks for In-Ga-Zn-O thin-film transistors (IGZO TFTs) under an overall low thermal budget (T = 150 °C). Characterization of the multicomponent layers and of the TFTs working characteristics (employing them) was performed in terms of static performance, reliability, and stability to understand the role of the incorporation of the high-κ material in the gate dielectric stack. It is shown that inherent disadvantages of the high-κ material, such as poorer interface properties and poor gate insulation, can be counterbalanced by inclusion of SiO2 both mixed with Ta2O5 and as thin interfacial layers. A stack comprising a (Ta2O5)x(SiO2)100 − x film with x = 69 and a thin SiO2 film at the interface with IGZO resulted in the best performing TFTs, with field-effect mobility (µFE) ≈ 16 cm2·V−1·s−1, subthreshold slope (SS) ≈ 0.15 V/dec and on/off ratio exceeding 107. Anomalous Vth shifts were observed during positive gate bias stress (PGBS), followed by very slow recoveries (time constant exceeding 8 × 105 s), and analysis of the stress and recovery processes for the different gate dielectric stacks showed that the relevant mechanism is not dominated by the interfaces but seems to be related to the migration of charged species in the dielectric. The incorporation of additional SiO2 layers into the gate dielectric stack is shown to effectively counterbalance this anomalous shift. This multilayered gate dielectric stack approach is in line with both the large area and the flexible electronics needs, yielding reliable devices with performance suitable for successful integration on new electronic applications.publishersversionpublishe

Low-temperature amorphous oxide semiconductors for thin-film transistors and memristors: physical insights and applications

While amorphous oxides semiconductors (AOS), namely InGaZnO (IGZO), have found market application in the display industry, their disruptive properties permit to envisage for more advanced concepts such as System-on-Panel (SoP) in which AOS devices could be used for addressing (and readout) of sensors and displays, for communication, and even for memory as oxide memristors are candidates for the next-generation memories. This work concerns the application of AOS for these applications considering the low thermal budgets (< 180 °C) required for flexible, low cost and alternative substrates. For maintaining low driving voltages, a sputtered multicomponent/multi-layered high-κ dielectric (Ta2O5+SiO2) was developed for low temperature IGZO TFTs which permitted high performance without sacrificing reliability and stability. Devices’ performance under temperature was investigated and the bias and temperature dependent mobility was modelled and included in TCAD simulation. Even for IGZO compositions yielding very high thermal activation, circuit topologies for counteracting both this and the bias stress effect were suggested. Channel length scaling of the devices was investigated, showing that operation for radio frequency identification (RFID) can be achieved without significant performance deterioration from short channel effects, which are attenuated by the high-κ dielectric, as is shown in TCAD simulation. The applicability of these devices in SoP is then exemplified by suggesting a large area flexible radiation sensing system with on-chip clock-generation, sensor matrix addressing and signal read-out, performed by the IGZO TFTs. Application for paper electronics was also shown, in which TCAD simulation was used to investigate on the unconventional floating gate structure. AOS memristors are also presented, with two distinct operation modes that could be envisaged for data storage or for synaptic applications. Employing typical TFT methodologies and materials, these are ease to integrate in oxide SoP architectures

Thin film engineering for transparent thin film transistors

Zinc oxide (ZnO) and Indium Gallium Zinc Oxide (IGZO) thin films are of interest as oxide semiconductors in thin film transistor (TFT) applications, due to visible light transparency, and low deposition temperature. There is particular interest in ZnO and IGZO based transparent TFT devices fabricated at low temperature on low cost flexible substrates. However, thermal annealing processes are typically required to ensure a good performance, suitable long term stability, and to control the point defects which affect the electrical characteristics. Hence there is interest in post deposition processing techniques, particularly where alternatives to high temperature thermal treatments can be utilised in combination with low temperature substrates. This thesis presents the results of a series of experimental studies as an investigation into photonic (excimer laser) processing of low temperature ZnO and IGZO thin films deposited by RF magnetron sputtering and/or by high target utilisation sputtering (HiTUS), to optimise the microstructure and electrical properties for potential use in thin film electronic applications. ZnO thin films were grown at various deposition parameters by varying oxygen flow rates, RF power, oxygen concentration, and growth temperatures

플라즈마 화학 기상 증착법을 이용한 베리어 필름 합성과 디스플레이 응용

학위논문 (박사)-- 서울대학교 대학원 : 자연과학대학 화학부, 2019. 2. 홍병희.자발광형 디스플레이이며, 저전압 구동이 가능하고 얇은 두께로 제작이 가능하며 동작속도가 매우 빠를 뿐만 아니라 높은 해상도 구현이 가능한 OLED는 디스플레이에서 빠른 성장세를 보이고 있다. 최근 OLED의 가장 큰 관심 분야는 모바일용 디스플레이와 대면적 TV, 그리고 플렉시블 및 투명 디스플레이 구현이다. 디스플레이를 구동하기 위한 구동소자는 수동형(passive matrix)과 능동형(active matrix, AM)로 나뉘며, 수동형에 비하여 고화질, 낮은 소비 전력, 대형화에 유리한 능동형 디스플레이가 선호된다. 표시소자를 능동 구동하기 위해서는 각 화소마다 박막 트랜지스터(thin-film transistor, TFT)와 같은 스위칭 소자를 부착시켜야 한다. 능동형 구동소자의 경우 현재의 TFT-LCD나 AMOLED용 백플레인에 주로 사용되는 비정질 실리콘(a-Si), 저온 다결정 실리콘 (LTPS) 기술이 우선 개발되어 응용되고 있다. 최근에는 큰 밴드 갭을 가지는 비정질 산화물 반도체를 이용해 투명하면서 빠른 응답속도의 디스플레이 구동소자에 대한 연구가 활발히 진행되고 있다. 또한 배선의 RC Delay를 최소화 시켜야 하고, 파워소비량을 줄여야 하는 기술적인 문제가 있다. 디스플레이의 고해상도인 UHD (Ultra High Definition)의 backplane에서 고속 TFT 구현을 위하여 SD(Source-Drain) 메탈 배선 구현은 필수적인 요소이다. 본 연구에서는 SD 메탈 배선으로써 저저항 배선인 Copper 배선의 diffusion barrier 역할을 하는 Graphite 성장을 다루고 있다. 기존의 Graphene 합성은 기계적 및 화학적 박리 방법에는 대면적 패널 구현으로써 한계가 있다. 현재까지 대형 Size scale Graphene 시도는 전극으로써 Graphene 활용은 있지만, 이 구현은 Thermal CVD (900~1000℃)에서 Graphene 을 합성하고, Glass에 transfer 한 논문으로써 실제 대면적으로 만드는 공정 적용에는 한계가 있다. 이에 현재 많이 연구는 진행 중이고 있지만, PECVD (Plasma Enhanced Chemical Vapor Deposition)를 이용한 graphite 박막 합성은 대형 size, mass production을 가능하게 하며, 아직 mass production 적용을 위해 연구해야 할 점은 많지만, 저온 공정 Graphite 합성이 가능하다면, large scale device 구현에 한층 더 진보된 기술이 될 것임을 확신한다. 본 연구에서 Copper diffusion barrier 으로써의 역할을 검증하고, 증착 온도를 저온으로 합성함으로써 TEM 및 EDAX 분석으로 Graphite barrier 및 mass production의 가능성을 검증하였다. 본 연구의 직접적인 PECVD 합성 방법을 통해 대면적이 가능함을 제시함으로써 기존의 대면적 합성 문제점을 해결해 줄 수 있는 방안이 될 것이다. 또한 디스플레이의 TFT 특성도 기존의 Active material 인 a-Si TFT보다 훨씬 더 높은 고이동도 소자를 요구하며, 특히 투명 디스플레이의 적용 가능하며, 고이동도 특성을 균일하게 가질 수 있는 신규 TFT를 요구하게 되었다. 이에 대한 방안으로 산화물 TFT로써 ZnO (Zinc Oxide), IZO (Indium Zinc Oxide), a-IGZO (Amorphous Indium Gallium Zinc Oxide) 등의 재료가 연구되고 있다. 기존의 a-Si의 이동도 (<1cm2/V·S) 보다 높은 이동도를 가진 IGZO 재료는 투명한 소자로써 투명디스플레이에서도 활용이 가능하여, 응용성을 확대하고 있다. 본 연구에서는 투명디스플레이 에서도 활용이 가능하도록 a-IGZO를 substrate로 하는 Graphite 박막을 합성 방법을 제시하고, 대면적 구현으로써 그 응용성을 기대하고 있다. Graphite의 저온 합성 기술 개발은 기존 라인의 CVD 장비 교체 없이 단지 Graphene Gas 사용만으로 공정을 구현한다는 점이 cost 및 공정 단순화의 관점에서 많은 장점이 있다. 또한 고속 구동을 위하여 SD 배선으로 metal뿐 아니라 산화물 반도체로도 Graphite 합성의 catalyst로써 사용되어, 패널 구현을 가능하게 해준다는 관점에서 의미가 있다. 또한 Graphite 합성 기술을 thin film 박막을 만들어 다른 application 에서도 활용 가능함을 보여줌으로써 파급 효과가 크다고 판단된다. 다음 연구에서는 LCD 디스플레이에서 Backlight 사용이 필수적이다. Back light는 가시광선 영역 뿐 아니라 UV 파장영역도 포함하고 있으며, Active 재료인 a-IGZO 소자에서 TFT 특성의 불안정성의 문제를 가지고 있다. IGZO의 특성상 UV 파장대에서의 빛과의 반응으로 TFT 소자의 신뢰성 특성이 악화되는 문제점을 해결하고자 Barrier 박막을 사용이 필수적인 요소이다. 본 연구에서는 TFT의 신뢰성 및 안정성을 유지하기 위해서 Photo blocking barrier로써 SiGe (Silicon Germanium) 박막 재료 합성을 통하여 TFT 신뢰성의 특성 변화 없는 것을 연구하였다. 이전 SiGe 연구되어진 바로는 태양전지에서 P-I(intrinsic layer)-N형 구조에서 중간 삽입층에서 불순물이 첨가되지 않은 무첨가층 (Intrinsic layer)에서 SiGe 이 광흡수층으로 사용되어진 연구가 있었다. 본 연구에서는 TFT 소자에서 a-IGZO 가 광반응으로 인해 산소 결핍 (Oxygen Vacancy)을 막아 TFT 특성의 저하 효과를 막고자 SiGe의 광 차단 박막 형성을 통해 광반응으로 인한a-IGZO특성 변화가 되지 않도록 하였다. 또한 박막 형성 및 적층 구조에서 SiGe 와 IGZO의 박막 사이에 Capacitance 형성으로 전자의 charge가 IGZO 박막 계면에 누적되어, 트랜지스터 특성이 단락(short) 현상이 발생 하였으며, 이를 방지하기 위해 Buffer layer 의 두께 조절이 중요하였다. 이에 Buffer layer의 두께 최적화를 통해 하부에서 들어오는 빛에도 차단을 할 수 있는 Barrier 적층 구조를 만들어 TFT 소자의 신뢰성 개선됨을 보여주고자 하였다. 스마트 Window 및 냉장고에서 문을 열지 않고 내용물을 확인할 수 있는 투명 디스플레이 및 플렉시블 디스플레이 구현을 위해 여러 요소의 기술 연구가 진행되고 있으며, 이 구현을 위해 본 연구의 Barrier 박막 구현은 필수적인 요소로 응용성이 확대되어 활용됨을 기대해 본다.OLED is a self-emissive display can be driven at low voltage and manufactured in a thin layer. In addition, this display operates at a very high speed and emit a color that can be rapidly implemented. Recently, OLEDs main interest is mobile screen, large screen TV, flexible and transparent display. The driving device for display is classified to the passive matrix and active matrix. Active matrix is preferred because of higher resolution, lower energy consumption, and large size screen. To apply active matrix on display device, a switching device such as thin-film transistor (TFT) is attached to each pixel. For active driving devices, amorphous silicon (a-Si) and low-temperature polycrystalline silicon (LTPS) technologies are applied in current TFT –LCD or AMOLED back frame. Recently, there is an ongoing research on using amorphous oxide semiconductors with large bandgaps to research transparent and fast responsive display driving devices. Moreover, RC delay has a technical problem that must be minimized and reduce power consumption. Implementation of Source Drain (SD) is a metal wiring essential element for high-speed TFT execution in high-resolution UHD (Ultra High Definition) displays backplane. In this study, the graphite growth plays the role of diffusion barrier of copper wiring that has low resistance wiring with SD metal wiring. The chemical and mechanical stripping methods of conventional graphene synthesis application on large area panels is limited. Up to now, the large size graphene has been used as an electrode, but this implementation is limited to making the large-scale process by synthesizing graphene at thermal CVD (900~1000°C) and transferring it to the glass. Despite the fact, a lot of ongoing studies, graphites thin film synthesis using Plasma Enhanced Chemical Vapor Deposition (PECVD) enables large size and mass production. Furthermore, this area still requires more research on mass production. If low-temperature process for graphite synthesis is possible, this will become a more advanced technology for device implementation. In this study, the role of copper diffusion barrier was verified, and the possibility of graphite barrier and mass production was verified by TEM and EDAX analysis by synthesizing the deposition temperature at low temperature. In addition, this study suggests the large size display can be obtained through direct PECVD synthesis that will solve the existing problems of large size synthesis. The displays TFT characteristics also require a high mobility device that is much higher than the conventional active material a-Si TFT. In particular, a new TFT capable of applying a transparent display and uniformly having high mobility characteristics is required. Materials such as ZnO (Zinc Oxide), IZO (Indium Zinc Oxide) and IGZO (Indium Gallium Zinc Oxide) have been studied as oxide TFTs. IGZO materials with higher mobility than conventional a-Si mobility (<1 cm2 / V · s) are transparent devices and can be used in transparent displays, thus extending applicability. In this study, we propose a graphite synthesis based on IGZO to be applicable to transparent display and expect the application on large size displays. The low-temperature Graphite synthesis has many advantages in terms of cost and process simplification because it implements the process only by using Graphene gas without replacing existing CVD equipment. In addition, it can be used as a graphite synthesis catalyst not only for metal but also for the oxide semiconductor, to raise activation. Moreover, the graphite synthesis to make a thin film can be applied to other fields. In the next study, it is essential to use backlight in LCD display. The backlight not only includes the visible light but also the UV region, and has instability of TFT characteristics in the active material IGZO device. Due to IGZOs reaction to light in UV region, it is essential to use a barrier film in order to solve the reliability characteristics of the TFT device deterioration. To maintain the reliability and stability of the TFT, this study on reliability of the TFT was not changed by SiGe (Silicon Germanium) synthesis thin film as a photo blocking barrier. Based on previous research on SiGe has been used as the light absorbing layer in the intrinsic layer in which a P-I (intrinsic layer)-N type structure in a solar cell that is not doped with an impurity in an intermediate insertion layer. In this study, in order to prevent oxygen vacancy during a-IGZO photoreaction on TFT device, the formation of a light-shielding film of Si-Ge prevents oxygen deficiency. Capacitance formation between SiGe and IGZO thin film in the thin film formation and lamination structure accumulates electrons charge on the IGZO thin film interface. The characteristics of the transistor were short, and to prevent this shortness, it is important to control the thickness of the buffer layer. Therefore, this shows that the reliability of the TFT device is improved by making the barrier laminate structure that can block the light from the bottom through the optimization of the thickness of the buffer layer. There are various ongoing technological studies on transparent and flexible displays that to observe the contents without opening the door through the smart window and refrigerator. For this application, the thin film barrier is an essential element and expect to be implemented.Table of Contents Abstract.........................................................................1 Contents........................................................................6 List of Figures.................................................................9 List of Tables................................................................15 Chapter 1. Introduction................................................16 1.1. Graphene characteristics 1.2. Amorphous Si:H and LTPS TFT backplane technology in display 1.3. High performance amorphous In-Ga-Zn-O TFTs 1.4. Overview of PECVD system 1.5. References Chapter 2. Growth of thin graphite films for solid diffusion barriers .......................................................60 2.1. Large-scale transfer-free growth of thin graphite films at low temperature for solid diffusion barriers 2.1.1. Introduction 2.1.2. Experimental 2.1.3. Results and discussion 2.1.4. Conclusion 2.1.5. References Chapter 3. Growth of silicon germanium films for photo-blocking layers in industrial display.................99 3.1. Silicon germanium photo-blocking layers for a-IGZO based industrial display 3.1.1. Introduction 3.1.2. Experimental 3.1.3. Results and Discussion 3.1.4. Conclusion 3.1.5. References Abstract in Korean………………………………………130 Appendix……………………………………………………135Docto

Process Investigations on Sputter Deposited Indium Tungsten Oxide TFT

Indium-Tungsten Oxide (IWO) has been investigated as a potential semiconductor material for next-generation display devices. Several publications have reported on IWO thin-film transistors (TFTs) with a channel mobility μch ~ 20cm2/Vs, approximately 2X higher than typically reported for Indium-Gallium-Zinc Oxide (IGZO). However, other attributes of the device characteristics have not performed as well as IGZO such as the subthreshold behavior. This work presents a study on the electronic properties of sputtered IWO, with the sputter ambient (i.e. percent O2 ) and O2 annealing conditions as the primary factors investigated. In the early stages of the study, a problem with the IWO target surface condition was found to be responsible for non-reproducible TFT properties. This initiated an extensive investigation on the details of target reconditioning, presputter conditions and reactive sputter ambient with oxygen. IWO sputter recipes and procedures were implemented which ensured consistent plasma characteristics and target surface condition. Reactive sputter conditions with low O2 content resulted in electrical behavior that was very different from argon-only sputtering (zero percent oxygen). IWO TFTs processed with 1.2% O2 sputter ambient, followed by O2 annealing at 300°C for 8-10 hours demonstrated promising current-voltage characteristics, with a low-field channel mobility μch ~ 18 cm2/Vs @ VDS = 0.1V. While higher oxygen content sputter conditions (10% O2) demonstrated a higher post-anneal resistivity, the device operation was inferior to the low oxygen treatment TFT. This was apparent in both on-state and off-state conditions, with the low oxygen treatment exhibiting higher current drive and steeper subthreshold. Increasing the O2 anneal temperature to 350°C on TFTs with the low oxygen treatment showed encouraging gate-controlled channel modulation for a 2 hour anneal. Raising this temperature to 400°C resulted in reduced gate control and current modulation, suggesting the onset of an additional defect mechanism. Degradation in device operation demonstrated by the high oxygen treatment as-sputtered material, or by aggressive O2 annealing at T \u3e 350°C, may have a similar origin

Interpretation and Physical Modeling of Electronic Transport and Defect States in IGZO Thin-Film Transistors

This work is a comprehensive study on the interpretation and modeling of electronic transport behavior and defect states in indium-gallium-zinc-oxide (IGZO) TFTs. Key studies have focused on advancing the state of IGZO TFTs by addressing several challenges in device stability, scaling, and device modeling. These studies have provided new insight on the associated mechanisms and have resulted in the realization of scaled thin-film transistors that exhibit excellent electrical performance and stability. This work has demonstrated the ability to scale the conventional inverted staggered IGZO TFT down to one micron channel length, with excellent on-state and off-state performance where the VT ≈1 V, µeff =12 cm2/Vs, Ileak ≤ 10-12 A/µm and SS ≈ 160 mV/dec. The working source/drain electrodes are direct metal contact regions to the IGZO, which requires several microns of gate overlap to provide ohmic behavior with minimal series resistance and ensure tolerance to overlay error. New results utilizing ion implantation for self-aligned source/drain regions present a path towards submicron channel length. This strategy offers a reduction in channel length as well as parasitic capacitance, which translates to improvement in RC delay and associated voltage losses due to charge-sharing. The realization of self-aligned TFTs using boron ion implantation for selective activation was introduced in a first-time report of boron-doped IGZO. Cryogenic measurements made on long-channel devices has revealed temperature-dependent behavior that is not explained by existing TCAD models employed for defect states and carrier mobility. A completely new device model using Silvaco Atlas has been established which properly accounts for the role of donor-like oxygen vacancy defects, acceptor-like band-tail states, acceptor-like interface traps, and a temperature-dependent intrinsic channel mobility. The developed model demonstrates a remarkable match to transfer characteristics measured at T = 150 K to room temperature. A power-law fit for the µch = f(T) relationship, which resembles 〖μ ~ T〗^((+3)⁄2) behavior consistent with ionized defect scattering. The mobility model is expressly independent of carrier concentration, without dependence on the applied gate bias. The device model is consistent with a compact model developed for circuit simulation (SPICE) that has been recently refined to include on-state and off-state operation. While IGZO is the only AOS technology mature enough for commercialization, the effective electron channel mobility µeff ~ 10 cm2/Vs presents a performance limitation. Other candidate AOS materials which have higher reported channel mobility values have also been investigated; specifically, indium-tungsten-oxide (IWO) and indium-gallium-tin-oxide (ITGO). These investigations serve as preliminary studies; device characteristics support the claims of high channel mobility; however the influence of defect states clearly indicates the need for further process development. The advancements realized in IGZO TFTs in this work will serve as a foundation for these alternative AOS materials

Solution-based IGZO nanoparticles memristor

This work aims to characterize Indium-Gallium-Zinc-Oxide nanoparticles (IGZOnp) as a resistive switching matrix in metal-insulator-metal (MIM) structures for memristor application. IGZOnp was produced by low cost solution-based process and deposited by spin-coating technique. Several top and bottom electrodes combinations, including IZO, Pt, Au, Ti, Ag were investigated to evaluate memory performance, yield and switching properties. The effect of ambient and annealing temperature using 350 ºC and 200 ºC was also analysed in order to get more insight into resistive switching mechanism. The Ag/IGZOnp/Ti memristor structure annealed at 200 ºC exhibits the best results with a large yield. The device shows a self-compliant bipolar resistive switching behavior. The switching event is achieved by the set/reset voltages of -1 V/+1 V respectively with an operating window of 10, and it can be programmed for more than 100 endurance cycles. The retention time of on and off-states is up to 104 s. The obtained results suggest that Ag/IGZOnp/Ti structure could be applied in system on a panel (SoP) as a viable device