A VHDL-AMS Based Time Domain Skin Depth Model for Edge Coupled Lossy Transmission Stripline

This contribution presents a time-domain model of the skin depth effect in a lossy transmission line. The model was developed and implemented in VHDL-AMS for a two wire edge coupled line but it is general and can be used for other types of lossy transmission line and high-frequency applications with skin depth effect. The salient feature of the model is the use of signal variation rate instead of frequency in the signal dependent resistance that models the skin depth losses. VHDL-AMS simulation experiments are presented to validate the model

Functional Verification of Large-integers Circuits using a Cosimulation-based Approach

Cryptography and computational algebra designs are complex systems based on modular arithmetic and build on multi-level modules where bit-width is generally larger than 64-bit. Because of their particularity, such designs pose a real challenge for verification, in part because large-integer’s functions are not supported in actual hardware description languages (HDLs), therefore limiting the HDL testbench utility. In another hand, high-level verification approach proved its efficiency in the last decade over HDL testbench technique by raising the latter at a higher abstraction level. In this work, we propose a high-level platform to verify such designs, by leveraging the capabilities of a popular tool (Matlab/Simulink) to meet the requirements of a cycle accurate verification without bit-size restrictions and in multi-level inside the design architecture. The proposed high-level platform is augmented by an assertion-based verification to complete the verification coverage. The platform experimental results of the testcase provided good evidence of its performance and re-usability

Automated UVM testbench generation

Abstract. This thesis studies the possibilities to automate UVM testbench creation in the telecommunications industry. First, the ideas behind UVM are looked at and automatable parts of the testbench coding process are studied. Facilitating the reuse of code is also examined. Development of an automation script with python for Nokia is covered in the work, and the possibilities for future improvements are discussedAutomatisoitu UVM testipenkin generointi. Tiivistelmä. Tämä kandidaatintyö tutkii mahdollisuuksia automatisoida UVM testipenkin kehitystä tietoliikennetekniikan saralla. Aluksi käydään läpi UVM:n taustaideat ja pohditaan automatisoitavia osia koodausprosessissa. Koodin uudelleenkäytettävyyttä tutkitaan myös tarkasti. Työssä käydään läpi automaatioskriptin kehitys Nokialle pythonilla ja mietitään mahdollisia suuntia jatkokehitykselle

SystemC-based Minimum Intrusive Fault Injection Technique with Improved Fault Representation

In this paper, we propose a new SystemC-based fault injection technique that has improved fault representation in visible and on-the-fly data and signal registers. The technique is minimum intrusive since it only requires replacing the original data or signal types to fault injection enabler types. We compare the proposed simulation technique with recently reported SystemC-based techniques and show that our technique has fast simulation speed, better fault representation, while maintaining simplicity and minimum intrusion. We demonstrate fault injection capabilities in a behavioural SystemC description of MPEG-2 decoder using proposed technique and show that up to 98.9% fault representation within data and signal registers can be achieved

A generic debug interface for IP-integrated assertions

Der Entwurf von Hardware/Software Systemen ist auf eine solide Verifikationsmethodik angewiesen, die den ganzen Design Flow durchzieht. Viele Konzepte haben eine Erhöhung des Abstraktionsniveaus bei der Entwurfseingabe gemeinsam, wobei der modell-basierte Hardware-Entwurf einen vielversprechenden und sich verbreitenenden Ansatz darstellt. Assertion basierte Verifikation ermöglicht dem Entwickler die Spezifikation von Eigenschaften des Entwurfes und die Aufdeckung von Fällen, in denen diese verletzt werden. Während Assertions in Entwurfs- und Simulationsstadien weit verbreitet sind, ist der Ansatz, diese mit auf dem integrierten Schaltkreis (IC) zu fertigen, neuartig. In dieser Diplomarbeit soll ein von Infineon Technologies entwickeltes, auf UML basierendes Datenmodell, welches zur Erfassung von Entwurfsspezifikation und zur automatischen Code-Generierung genutzt wird dahingehend erweitert werden, die Beschreibung für im IC integrierte Assertions zu ermöglichen. Für diese Zwecke wird ein abstraktes Datenmodell beschrieben werden. Das Assertion Interface soll die spezifikationsgetreue Modellintegration gewährleisten, sowie IC interne Assertionresultate dem umgebenen System über das Interface zugänglich machen und damit zum Debugging während der Laufzeit ermöglichen. Ferner werden die Codegenerierungs Templates erläutert und einBeispielsystem eingeführt, um die beschriebenden Konzepte zu validieren.Nowadays electronic systems design requires fast time to market and solid verification throughout the entire design flow. Many concepts have been researched to raise the level of abstraction during the design entry phase, whereas model-based design is the most promising one. Assertion-based verification enables the developer to specify properties of the design and to get report if these are violated. Assertions are common during development and simulation of electronic products but often are not included in the final silicon. In this thesis an UML-based model defined at Infineon Technologies for capturing design specification information and to generate code automatically using templates, will be extended to allow the description of an abstract debuggable assertion interface for silicon assertions. With help of the assertion interface it shall be possible to verify the correct module integration and to monitor IP-internal assertion checker results. Besides, the code-generation templates for the assertion interface model will be described. To demonstrate the usability of the developed concepts an example system will be introduced to validate the approach.Ilmenau, Techn. Univ., Diplomarbeit, 200

On mixed abstraction, languages and simulation approach to refinement with SystemC AMS

Executable specifications and simulations arecornerstone to system design flows. Complex mixed signalembedded systems can be specified with SystemC AMSwhich supports abstraction and extensible models of computation. The language contains semantics for moduleconnections and synchronization required in analog anddigital interaction. Through the synchronization layer, user defined models of computation, solvers and simulators can be unified in the SystemC AMS simulator for achieving low level abstraction and model refinement. These improvements assist in amplifying model aspects and their contribution to the overall system behavior. This work presents cosimulating refined models with timed data flow paradigm of SystemC AMS. The methodology uses Cbased interaction between simulators. An RTL model ofdata encryption standard is demonstrated as an example.The methodology is flexible and can be applied in earlydesign decision trade off, architecture experimentation and particularly for model refinement and critical behavior analysis

Hardware Acceleration Using Functional Languages

Cílem této práce je prozkoumat možnosti využití funkcionálního paradigmatu pro hardwarovou akceleraci, konkrétně pro datově paralelní úlohy. Úroveň abstrakce tradičních jazyků pro popis hardwaru, jako VHDL a Verilog, přestáví stačit. Pro popis na algoritmické či behaviorální úrovni se rozmáhají jazyky původně navržené pro vývoj softwaru a modelování, jako C/C++, SystemC nebo MATLAB. Funkcionální jazyky se s těmi imperativními nemůžou měřit v rozšířenosti a oblíbenosti mezi programátory, přesto je předčí v mnoha vlastnostech, např. ve verifikovatelnosti, schopnosti zachytit inherentní paralelismus a v kompaktnosti kódu. Pro akceleraci datově paralelních výpočtů se často používají jednotky FPGA, grafické karty (GPU) a vícejádrové procesory. Praktická část této práce rozšiřuje existující knihovnu Accelerate pro počítání na grafických kartách o výstup do VHDL. Accelerate je možno chápat jako doménově specifický jazyk vestavěný do Haskellu s backendem pro prostředí NVIDIA CUDA. Rozšíření pro vysokoúrovňovou syntézu obvodů ve VHDL představené v této práci používá stejný jazyk a frontend.The aim of this thesis is to research how the functional paradigm can be used for hardware acceleration with an emphasis on data-parallel tasks. The level of abstraction of the traditional hardware description languages, such as VHDL or Verilog, is becoming to low. High-level languages from the domains of software development and modeling, such as C/C++, SystemC or MATLAB, are experiencing a boom for hardware description on the algorithmic or behavioral level. Functional Languages are not so commonly used, but they outperform imperative languages in verification, the ability to capture inherent paralellism and the compactness of code. Data-parallel task are often accelerated on FPGAs, GPUs and multicore processors. In this thesis, we use a library for general-purpose GPU programs called Accelerate and extend it to produce VHDL. Accelerate is a domain-specific language embedded into Haskell with a backend for the NVIDIA CUDA platform. We use the language and its frontend, and create a new backend for high-level synthesis of circuits in VHDL.

UVM testbench in Python:feature and performance comparison with SystemVerilog implementation

Abstract. Python is emerging as a new language for functional verification of digital integrated circuits (ICs). With the Python verification framework cocotb enabling to write testbenches in Python, new libraries are being developed for various verification techniques and methodologies, such as functional coverage, constrained random verification and Universal Verification Methodology (UVM). Python testbenches have been used in some research and product development, but there is little information available on their performance, and no studies about applying UVM in Python have been published. In this thesis, a Python UVM testbench was developed using pyuvm and other Python verification libraries for an AHB-Lite slave IP, and a matching testbench in SystemVerilog was also built to examine the differences in their implementations. Testbench codebase sizes, simulation execution times, memory use and coverage accumulation were compared. The Python testbench had 30% less lines of code, suggesting that testbench development may be faster in Python than SystemVerilog. The execution times of the Python testbench on commercial simulators were 8 to 21 times longer than those of the SystemVerilog testbench in tests with AHB-Lite write operations and random stimulus. In conclusion, given the performance gap and the UVM Register Abstraction Layer (RAL) being at an early stage of development in pyuvm, the studied Python libraries are not competitive with SystemVerilog and its UVM implementation for verifying complex designs like systems-on-chip (SoCs) at this stage. Nevertheless, pyuvm enables Python programmers and users of open-source simulators without support for SystemVerilog UVM to start using the methodology. A Python UVM testbench based on pyuvm is currently viable for verifying simple designs, and it opens new avenues of research in digital IC verification.Tiivistelmä. Python on nousemassa uudeksi kieleksi digitaalisten integroitujen piirien varmennukseen. Cocotb-viitekehys mahdollistaa testipenkkien kirjoittamisen Pythonilla, ja uusia Python-kirjastoja kehitetään eri varmennusmenetelmille, kuten funktionaaliselle kattavuudelle, rajoitetulla satunnaisherätteellä verifioinnille ja universaalille varmennusmenetelmälle (engl. Universal Verification Methodology, UVM). Python-testipenkkejä on pienissä määrin käytetty tutkimuksissa ja tuotekehityksessä, mutta niiden suorituskyvystä on hyvin vähän tietoa, ja UVM:n käytöstä Pythonilla ei ole julkaistu tutkimuksia. Tässä työssä kehitettiin UVM-testipenkki Pythonilla AHB-Lite-orjana toimivalle IP-lohkolle käyttäen pyuvm:ää ja muita Python-verifiointikirjastoja, ja vastaava testipenkki luotiin myös SystemVerilogilla toteutusten vertailua varten. Testipenkeistä verrattiin koodikannan kokoa, suoritusaikaa, muistin käyttöä ja kattavuuden kertymistä. Python-testipenkissä oli 30 % vähemmän koodirivejä, mikä voi merkitä, että testipenkkien kehittäminen Pythonilla on nopeampaa kuin SystemVerilogilla. Suoritusajat kaupallisilla simulaattoreilla oli Python-testipenkillä 8–21 kertaa pidempiä kuin SystemVerilog-testipenkillä testeissä, joissa ajettiin AHB-Lite -kirjoitusoperaatioita ja satunnaisherätettä. Koska suorituskykyero oli näin merkittävä, ja koska UVM:n rekisteriabstraktiotaso (engl. Register Abstraction Layer, RAL) on vasta alkutekijöissään pyuvm:ssä, voidaan todeta, että tutkitut Python-kirjastot eivät ole vielä nykyisellä tasollaan kilpailukykyisiä SystemVerilogin ja sen UVM-implementaation kanssa monimutkaisten piirien kuten järjestelmäpiirien varmennukseen. Siitä huolimatta pyuvm mahdollistaa UVM:n käytön Python-ohjelmoijille ja avoimen lähdekoodin simulaattoreissa, joissa ei ole vielä SystemVerilog UVM:lle tukea. Pyuvm-pohjainen Python UVM-testipenkki soveltuu tällä hetkellä yksinkertaisten mallien varmennukseen ja avaa uusia tutkimussuuntia digitaalisten integroitujen piirien varmennukseen