Distributed real-time operating system (DRTOS) modeling in SpecC

System level design of an embedded computing system involves a multi-step process to refine the system from an abstract specification to an actual implementation by defining and modeling the system at various levels of abstraction. System level design supports evaluating and optimizing the system early in design exploration.;Embedded computing systems may consist of multiple processing elements, memories, I/O devices, sensors, and actors. The selection of processing elements includes instruction-set processors and custom hardware units, such as application specific integrated circuit (ASIC) and field programmable gate array (FPGA). Real-time operating systems (RTOS) have been used in embedded systems as an industry standard for years and can offer embedded systems the characteristics such as concurrency and time constraints. Some of the existing system level design languages, such as SpecC, provide the capability to model an embedded system including an RTOS for a single processor. However, there is a need to develop a distributed RTOS modeling mechanism as part of the system level design methodology due to the increasing number of processing elements in systems and to embedded platforms having multiple processors. A distributed RTOS (DRTOS) provides services such as multiprocessor tasks scheduling, interprocess communication, synchronization, and distributed mutual exclusion, etc.;In this thesis, we develop a DRTOS model as the extension of the existing SpecC single RTOS model to provide basic functionalities of a DRTOS implementation, and present the refinement methodology for using our DRTOS model during system level synthesis. The DRTOS model and refinement process are demonstrated in the SpecC SCE environment. The capabilities and limitations of the DRTOS modeling approach are presented

Real-Time Operating Systems and Programming Languages for Embedded Systems

In this chapter, we present the different alternatives that are available today for the development of real-time embedded systems. In particular, we will focus on the programming languages use like C++, Java and Ada and the operating systems like Linux-RT, FreeRTOS, TinyOS, etc. In particular we will analyze the actual state of the art for developing embedded systems under the WORA paradigm with standard Java [1], its Real-Time Specification and with the use of Real-Time Core Extensions and pico Java based CPUs [5]. We expect the reader to have a clear view of the opportunities present at the moment of starting a design with its pros and cons so it can choose the best one to fit its case.Fil: Orozco, Javier Dario. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; Argentina. Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Laboratorio de Sistemas Digitales; ArgentinaFil: Santos, Rodrigo Martin. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; Argentina. Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Laboratorio de Sistemas Digitales; Argentin

Time-triggered State-machine Reliable Software Architecture for Micro Turbine Engine Control

AbstractTime-triggered (TT) embedded software pattern is well accepted in aerospace industry for its high reliability. Finite-state-machine (FSM) design method is widely used for its high efficiency and predictable behavior. In this paper, the time-triggered and state-machine combination software architecture is implemented for a 25 kg thrust micro turbine engine (MTE) used for unmanned aerial vehicle (UAV) system; also model-based-design development workflow for airworthiness software directive DO-178B is utilized. Experimental results show that time-triggered state-machine software architecture and development method could shorten the system development time, reduce the system test cost and make the turbine engine easily comply with the airworthiness rules

Modeling of Preemptive RTOS Scheduler with Priority Inheritance

This work describes an approach to generate accurate system-level model of embedded software on a targeted Real-Time Operating System (RTOS). We design a RTOS emulation layer, called RTOS_SC, on top of the SystemC kernel. The system level model can be used for software optimization in the early stage of a processor design. The model precision is obtained by integrating key features which are provided in typical RTOS schedulers. We first discuss a case study which shows the impact of the implemented features on a priority-driven scheduler. We then present the abstraction of tasks scheduling and communication mechanisms. To validate the accuracy of our model we use the tasks response time metric with industrial-size examples such as MP3, Vocoder and Jpeg encoder. The experimental results show a significant improvement compared to existing RTOS models

Hybrid prototyping of multicore embedded systems

Multicore platforms are becoming increasingly pervasive in modern embedded systems. System level modeling techniques have enabled creation of fast software models of multicore platforms, commonly known as Virtual Prototypes, for early functional validation of embedded software, before the hardware is available. On the other hand, for accurate performance validation, the complete multicore platform can be implemented as a physical prototype on FPGA. Both virtual platforms and FPGA prototypes have their respective pros and cons. Virtual platforms have the advantage of high speed functional simulation and, typically, scale well with the number of cores. However, the accuracy of performance estimation is sacrificed. FPGA prototypes provide cycle-accurate performance estimation, because the software executes directly on an FPGA implementation of the target cores. However, it takes a significant amount of time to design, implement and test the inter-core communication architecture on the FPGA. In this thesis we propose to design a novel system-level modeling framework, called Hybrid Prototyping. Our goal is to provide the benefits of both virtual platforms and FPGA prototypes. It aims to provide early, fast, and scalable models, similar to virtual platforms, along with the cycle-accuracy of FPGA prototypes. Using hybrid prototyping, embedded software designers will be able to create concurrent applications and accurately analyze the performance implication of their optimizations before the chip is delivered. At the same time, multicore architects will be able to modify the platform model without having to do full system prototyping. Therefore, hybrid prototyping will enable early and reliable multicore embedded system design, resulting in huge productivity gains for both embedded software designers and multicore chip architects

Reducing Transport Latency for Short Flows with Multipath TCP

Multipath TCP (MPTCP) has been an emerging transport protocol that provides network resilience to failures and improves throughput by splitting a data stream into multiple subflows across all the available multiple paths. While MPTCP is generally beneficial for throughput-sensitive large flows with large number of subflows, it may be harmful for latency-sensitive small flows. MPTCP assigns each subflow a congestion window, making short flows susceptible to timeout when a flow only contains a few packets. This condition becomes even worse when the paths have heterogeneous characteristics as packet reordering occurs and the slow paths can be used with MPTCP, causing the increased end-to-end delay and the lower application Goodput. Thus, it is important to choose the appropriate subflows for each MPTCP connection to achieve the good performance. However, the subflows in MPTCP are determined before a connection is established, and they usually remain unchanged during the lifetime of that connection. To address this issue, we propose DMPTCP, which dynamically adjusts the subflows according to application workloads. Specifically, DMPTCP first utilizes the idea of TCP modeling to estimate the latency on the path under scheduling and the data amount sent on the other paths simultaneously, and then decides the set of subflows to be used for certain application periodically with the goal of reducing completion time for short flows and achieving a higher throughput for long flows. We implement DMPTCP in a Linux server and conduct extensive experiments both in NS3 and in Linux testbed to validate its effectiveness. Our evaluation shows that DMPTCP decreases the completion time by over 46.55% compared to conventional MPTCP for short flows while increases the Goodput up to 21.3% for long-lived flows