Wideband integrated circuits for optical communication systems

The exponential growth of internet traffic drives datacenters to constantly improvetheir capacity. Several research and industrial organizations are aiming towardsTbps Ethernet and beyond, which brings new challenges to the field of high-speedbroadband electronic circuit design. With datacenters rapidly becoming significantenergy consumers on the global scale, the energy efficiency of the optical interconnecttransceivers takes a primary role in the development of novel systems. Furthermore,wideband optical links are finding application inside very high throughput satellite(V/HTS) payloads used in the ever-expanding cloud of telecommunication satellites,enabled by the maturity of the existing fiber based optical links and the hightechnology readiness level of radiation hardened integrated circuit processes. Thereare several additional challenges unique in the design of a wideband optical system.The overall system noise must be optimized for the specific application, modulationscheme, PD and laser characteristics. Most state-of-the-art wideband circuits are builton high-end semiconductor SiGe and InP technologies. However, each technologydemands specific design decisions to be made in order to get low noise, high energyefficiency and adequate bandwidth. In order to overcome the frequency limitationsof the optoelectronic components, bandwidth enhancement and channel equalizationtechniques are used. In this work various blocks of optical communication systems aredesigned attempting to tackle some of the aforementioned challenges. Two TIA front-end topologies with 133 GHz bandwidth, a CB and a CE with shunt-shunt feedback,are designed and measured, utilizing a state-of-the-art 130 nm InP DHBT technology.A modular equalizer block built in 130 nm SiGe HBT technology is presented. Threeultra-wideband traveling wave amplifiers, a 4-cell, a single cell and a matrix single-stage, are designed in a 250 nm InP DHBT process to test the limits of distributedamplification. A differential VCSEL driver circuit is designed and integrated in a4x 28 Gbps transceiver system for intra-satellite optical communications based in arad-hard 130nm SiGe process

Broadband Receiver Electronic Circuits for Fiber-Optical Communication Systems

The exponential growth of internet traffic drives datacenters to constantly improve their capacity. As the copper based network infrastructure is being replaced by fiber-optical interconnects, new industrial standards for higher datarates are required. Several research and industrial organizations are aiming towards 400 Gb Ethernet and beyond, which brings new challenges to the field of high-speed broadband electronic circuit design. Replacing OOK with higher M-ary modulation formats and using higher datarates increases network capacity but at the cost of power. With datacenters rapidly becoming significant energy consumers on the global scale, the energy efficiency of the optical interconnect transceivers takes a primary role in the development of novel systems. There are several additional challenges unique in the design of a broadband shortreach fiber-optical receiver system. The sensitivity of the receiver depends on the noise performance of the PD and the electronics. The overall system noise must be optimized for the specific application, modulation scheme, PD and VCSEL characteristics. The topology of the transimpedance amplifier affects the noise and frequency response of the PD, so the system must be optimized as a whole. Most state-of-the-art receivers are built on high-end semiconductor SiGe and InP technologies. However, there are still several design decisions to be made in order to get low noise, high energy efficiency and adequate bandwidth. In order to overcome the frequency limitations of the optoelectronic components, bandwidth enhancement and channel equalization techniques are used. In this work several different blocks of a receiver system are designed and characterized. A broadband, 50 GHz bandwidth CB-based TIA and a tunable gain equalizer are designed in a 130 nm SiGe BiCMOS process. An ultra-broadband traveling wave amplifier is presented, based on a 250 nm InP DHBT technology demonstrating a 207 GHz bandwidth. Two TIA front-end topologies with 133 GHz bandwidth, a CB and a CE with shunt-shunt feedback, based on a 130 nm InP DHBT technology are designed and compared

DESIGN OF A GAAS DISTRIBUTED AMPLIFIER WITH LC TRAPS BASED BROADBAND LINEARIZATION

Increasing the linearity of power amplifiers has been an important area of research because its signal integrity influences the performance of the entire transreceiver system and there are strict regulatory requirements on them. Due to the nonlinear behaviour of power amplifiers, third order intermodulation products are generated close to the desired signals and cannot be removed by filters. Increasing linearity will help bring these distortion products closer to the noise floor. However, it is not an easy task to increase linearity without trading off output power. To maintain the same level of output power generated but with higher linearity, many techniques, each with its own pros and cons, have been implemented to linearize an amplifier. Techniques involving feedback are seriously limited in terms of modulation bandwidth whereas methods such as predistortion and feedforward are very difficult to implement. This project seeks to use a simple method of placing terminations directly to the distributed amplifier (DA), making it a device level linearization technique and can be used in addition to the other system level techniques mentioned earlier. To increase linearity over a broad bandwidth of 0.5 to 3.0 GHz, this work proposes using low impedance terminations (LC traps) at the envelope frequency to the input and output of several distributed amplifiers. This research is novel since this is the first time broadband improvement in linearity has been demonstrated using the LC trap method. Two design iterations were completed (first design iteration has four variants to test the output trap while the second design iteration has three variants to test the input trap). The low impedance terminations are implemented using inductor-capacitor networks that are external to the monolithic microwave integrated circuit (MMIC). Design and layout of the DAs were carried out using Agilent’s Advanced Design System (ADS). Results show that placing the traps at the output of the DA does not truly affect the linearity of the device at lower frequencies but provide an improvement of 1.6 dB and 3.4 dB to the third-order output intercept point (OIP3) at 2.5 GHz and 3.0 GHz, respectively. With traps at the input, measurement results at -5 dBm input power, viii 1.375 V base bias (61 mA total collector current) and 10 MHz two tone spacing show a broadband improvement throughout the band (0.5 GHz to 3.0 GHz) of 3.3 dB to 7.4 dB in OIP3. Furthermore, the OIP3 is increased to 19.2 dB above P1dB. Results show that the improvement in OIP3 comes without lowering gain, return loss or P1dB and without causing any stability problems

Improving linearity utilising adaptive predistortion for power amplifiers at mm-wave frequencies

The large unlicensed 3 GHz overlapping bandwidth that is available worldwide at 60 GHz has resulted in renewed interest in 60 GHz technology. This frequency band has made it attractive for short-range gigabit wireless communication. The power amplifier (PA) directly influences the performance and quality of this entire communication chain, as it is one of the final subsystems in the transmitter. Spectral efficient modulation schemes used at 60 GHz pose challenging requirements for the linearity of the PA. To improve the linearity, several external linearisation techniques currently exist, such as feedback, feedforward, envelope elimination and restoration, linear amplification with non-linear components and predistortion. This thesis is aimed at investigating and characterising the distortion components found in PAs at mm-wave frequencies and evaluating whether an adaptive predistortion (APD) linearisation technique is suitable to reduce these distortion components. After a thorough literature study and mathematical analysis, it was found that the third-order intermodulation distortion (IMD3) components were the most severe distortion components. Predistortion was identified as the most effective linearisation technique in terms of minimising these IMD3 components and was therefore proposed in this research. It does not introduce additional complexity and can easily be integrated with the PA. Furthermore, the approach is stable and has lower power consumption when compared to the aforementioned linearisation techniques. The proposed predistortion technique was developed compositely through this research by making it a function of the PA’s output power that was measured using a power detector. A comparator was used with the detected output power and the reference voltages to control the dynamic bias circuit of the variable gain amplifier. This provided control and flexibility on when to apply the predistortion to the PA and therefore allowing the linearity of the PA to be optimised. Three-stage non-linear and linear PAs were also designed at 60 GHz and implemented to compare the performance of the APD technique and form part of the hypothesis verification process. The 130 nm silicon-germanium (SiGe) bipolar and complementary metal oxide semiconductor (BiCMOS) technology from IBM was used for the simulation of the entire APD and PA design and for the fabrication of the prototype integrated circuits (ICs). This technology has the advantage of integrating the high performance, low power intensive SiGe heterojunction bipolar transistors (HBTs) with the CMOS technology. The SiGe HBTs have a high cut-off frequency (fT > 200 GHz), which is ideal for mm-wave PA applications and the CMOS components were integrated in the control logic of the digital circuitry. The simulations and IC layout were accomplished with Cadence Virtuoso. The implemented IC occupies an area of 1.8 mm by 2.0 mm. The non-linear PA achieves a Psat of 11.97 dBm and an IP1dB of -10 dBm. With the APD technique applied, the linearity of the PA is significantly improved with an IP1dB of -6 dBm and an optimum IMD3 reduction of 10 dB. Based on the findings and results of the applied APD technique, APD reduced intermodulation distortion (especially the IMD3) and is thus suitable to improve the linearity of PAs at mm-wave frequencies. To the knowledge of this author, no APD technique has been applied for PAs at 60 GHz, therefore the contribution of this research will assist future PA designers to characterise and optimise the reduction of the IMD3 components. This will result in improved linear output power from the PA and the use of complex modulation schemes at 60 GHz.Thesis (PhD)--University of Pretoria, 2014.Electrical, Electronic and Computer EngineeringPh

SiGe-based broadband and high suppression frequency doubler ICs for wireless communications

制度:新 ; 報告番号:甲3419号 ; 学位の種類:博士(工学) ; 授与年月日:2011/9/15 ; 早大学位記番号:新574

Four-element phased-array beamformers and a self-interference canceling full-duplex transciver in 130-nm SiGe for 5G applications at 26 GHz

This thesis is on the design of radio-frequency (RF) integrated front-end circuits for next generation 5G communication systems. The demand for higher data rates and lower latency in 5G networks can only be met using several new technologies including, but not limited to, mm-waves, massive-MIMO, and full-duplex. Use of mm-waves provides more bandwidth that is necessary for high data rates at the cost of increased attenuation in air. Massive-MIMO arrays are required to compensate for this increased path loss by providing beam steering and array gain. Furthermore, full duplex operation is desirable for improved spectrum efficiency and reduced latency. The difficulty of full duplex operation is the self-interference (SI) between transmit (TX) and receive (RX) paths. Conventional methods to suppress this interference utilize either bulky circulators, isolators, couplers or two separate antennas. These methods are not suitable for fully-integrated full-duplex massive-MIMO arrays. This thesis presents circuit and system level solutions to the issues summarized above, in the form of SiGe integrated circuits for 5G applications at 26 GHz. First, a full-duplex RF front-end architecture is proposed that is scalable to massive-MIMO arrays. It is based on blind, RF self-interference cancellation that is applicable to single/shared antenna front-ends. A high resolution RF vector modulator is developed, which is the key building block that empowers the full-duplex frontend architecture by achieving better than state-of-the-art 10-b monotonic phase control. This vector modulator is combined with linear-in-dB variable gain amplifiers and attenuators to realize a precision self-interference cancellation circuitry. Further, adaptive control of this SI canceler is made possible by including an on-chip low-power IQ downconverter. It correlates copies of transmitted and received signals and provides baseband/dc outputs that can be used to adaptively control the SI canceler. The solution comes at the cost of minimal additional circuitry, yet significantly eases linearity requirements of critical receiver blocks at RF/IF such as mixers and ADCs. Second, to complement the proposed full-duplex front-end architecture and to provide a more complete solution, high-performance beamformer ICs with 5-/6- b phase and 3-/4-b amplitude control capabilities are designed. Single-channel, separate transmitter and receiver beamformers are implemented targeting massive- MIMO mode of operation, and their four-channel versions are developed for phasedarray communication systems. Better than state-of-the-art noise performance is obtained in the RX beamformer channel, with a full-channel noise figure of 3.3 d

Silicon Germanium BiCMOS Integrated Circuits for Scalable Cryogenic Sensing Applications

This dissertation is focused on an investigation of BiCMOS cryogenic low noise amplifiers (LNAs) based on Silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) for simultaneous low noise and low power design and also taking advantage of CMOS circuitry for adding flexibility to the LNA design. Cryogenic LNAs\u27 scalability challenges are discussed and addressed in the dissertation. To achieve that, first, HBTs of three state-of-the-art technologies are characterized and modeled at cryogenic temperature. It is shown that SiGe HBT provides a promising compromise of noise temperature, power consumption, and bandwidth. Moreover, a scalable on-chip approach is proposed and verified for biasing of SiGe HBTs based LNAs. Finally, the first cryogenic re-configurable LNA is designed, implemented, and measured

Radio Frequency and Millimeter Wave Circuit Component Design with SiGe BiCMOS Technology

The objective of this research is to study and leverage the unique properties and advantages of silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) integrated circuit technologies to better design radio frequency (RF) and millimeter wave (mm-wave) circuit components. With recent developments, the high yield and modest cost silicon-based semiconductor technologies have proven to be attractive and cost-effective alternatives to high-performance III-V technology platforms. Between SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) technology and advanced RF complementary metal-oxide-semiconductor (CMOS) technology, the fundamental device-level differences between SiGe HBTs and field-effect transistors (FETs) grant SiGe HBTs clear advantages as well as unique design concerns. The work presented in this dissertation identifies several advantages and challenges on design using SiGe HBTs and provides design examples that exploit and address these unique benefits and problems with circuit component designs using SiGe HBTs.Ph.D