NASA Ares 1 Crew Launch Vehicle Upper Stage Configuration Selection Process

The Upper Stage Element of NASA s Ares I Crew Launch Vehicle (CLV) is a "clean-sheet" approach that is being designed and developed in-house, with Element management at MSFC. The USE concept is a self-supporting cylindrical structure, approximately 115 long and 216" in diameter. While the Reusable Solid Rocket Booster (RSRB) design has changed since the CLV inception, the Upper Stage Element design has remained essentially a clean-sheet approach. Although a clean-sheet upper stage design inherently carries more risk than a modified design, it does offer many advantages: a design for increased reliability; built-in extensibility to allow for commonality/growth without major redesign; and incorporation of state-of-the-art materials, hardware, and design, fabrication, and test techniques and processes to facilitate a potentially better, more reliable system

Smart and high-performance digital-to-analog converters with dynamic-mismatch mapping

The trends of advanced communication systems, such as the high data rate in multi-channel base-stations and digital IF conversion in software-defined radios, have caused a continuously increasing demand for high performance interface circuits between the analog and the digital domain. A Digital-to-Analog converter (DAC) is such an interface circuit in the transmitter path. High bandwidth, high linearity and low noise are the main design challenges in high performance DACs. Current-steering is the most suitable architecture to meet these performance requirements. The aim of this thesis is to develop design techniques for high-speed high-performance Nyquist current-steering DACs, especially for the design of DACs with high dynamic performance, e.g. high linearity and low noise. The thesis starts with an introduction to DACs in chapter 2. The function in time/frequency domain, performance specifications, architectures and physical implementations of DACs are brie y discussed. Benchmarks of state-of-the-art published Nyquist DACs are also given. Chapter 3 analyzes performance limitations by various error sources in Nyquist current-steering DACs. The outcome shows that in the frequency range of DC to hundreds of MHz, mismatch errors, i.e. amplitude and timing errors, dominate the DAC linearity. Moreover, as frequencies increase, the effect of timing errors becomes more and more dominant over that of amplitude errors. Two new parameters, i.e. dynamic-INL and dynamic-DNL, are proposed to evaluate the matching of current cells. Compared to the traditional static-INL/DNL, the dynamic-INL/DNL can describe the matching between current cells more accurately and completely. By reducing the dynamic-INL/DNL, the non-linearities caused by all mismatch errors can be reduced. Therefore, both the DAC static and dynamic performance can be improved. The dynamic-INL/DNL are frequency-dependent parameters based on the measurement modulation frequency fm. This fm determines the weight between amplitude and timing errors in the dynamic-INL/DNL. Actually, this gives a freedom to optimize the DAC performance for different applications, e.g. low fm for low frequency applications and high fm for high frequency applications. Chapter 4 summarizes the existing design techniques for intrinsic and smart DACs. Due to technology limitations, it is diffcult to reduce the mismatch errors just by intrinsic DAC design with reasonable chip area and power consumption. Therefore, calibration techniques are required. An intrinsic DAC with calibration is called a smart DAC. Existing analog calibration techniques mainly focus on current source calibration, so that the amplitude error can be reduced. Dynamic element matching is a kind of digital calibration technique. It can reduce the non-linearities caused by all mismatch errors, but at the cost of an increased noise oor. Mapping is another kind of digital calibration technique and will not increase the noise. Mapping, as a highly digitized calibration technique, has many advantages. Since it corrects the error effects in the digital domain, the DAC analog core can be made clean and compact, which reduces the parasitics and the interference generated in the analog part. Traditional mapping is static-mismatch mapping, i.e. mapping only for amplitude errors, which many publications have already addressed on. Several concepts have also been proposed on mapping for timing errors. However, just mapping for amplitude or timing error is not enough to guarantee a good performance. This work focuses on developing mapping techniques which can correct both amplitude and timing errors at the same time. Chapter 5 introduces a novel mapping technique, called dynamic-mismatch mapping (DMM). By modulating current cells as square-wave outputs and measuring the dynamic-mismatch errors as vectors, DMM optimizes the switching sequence of current cells based on dynamic-mismatch error cancelation such that the dynamic-INL can be reduced. After reducing the dynamic-INL, the non-linearities caused by both amplitude and timing errors can be significantly reduced in the whole Nyquist band, which is confirmed by Matlab behavioral-level Monte-Carlo simulations. Compared to traditional static-mismatch mapping (SMM), DMM can reduce the non-linearities caused by both amplitude and timing errors. Compared to dynamic element matching (DEM), DMM does not increase the noise floor. The dynamic-mismatch error has to be accurately measured in order to gain the maximal benefit from DMM. An on-chip dynamic-mismatch error sensor based on a zero-IF receiver is proposed in chapter 6. This sensor is especially designed for low 1/f noise since the signal is directly down-converted to DC. Its signal transfer function and noise analysis are also given and con??rmed by transistor-level simulations. Chapter 7 gives a design example of a 14-bit current-steering DAC in 0.14mum CMOS technology. The DAC can be configured in an intrinsic-DAC mode or a smart-DAC mode. In the intrinsic-DAC mode, the 14-bit 650MS/s intrinsic DAC core achieves a performance of SFDR>65dBc across the whole 325MHz Nyquist band. In the smart-DAC mode, compared to the intrinsic DAC performance, DMM improves the DAC performance in the whole Nyquist band, providing at least 5dB linearity improvement at 200MS/s and without increasing the noise oor. This 14-bit 200MS/s smart DAC with DMM achieves a performance of SFDR>78dBc, IM

Improving the management of non-ST elevation acute coronary syndromes: systematic evaluation of a quality improvement programme European QUality Improvement Programme for Acute Coronary Syndrome: The EQUIP-ACS project protocol and design

Acute coronary syndromes, including myocardial infarction and unstable angina, are important causes of premature mortality, morbidity and hospital admissions. Acute coronary syndromes consume large amounts of health care resources, and have a major negative economic and social impact through days lost at work, support for disability, and coping with the psychological consequences of illness. Several registries have shown that evidence based treatments are under-utilised in this patient population, particularly in high-risk patients. There is evidence that systematic educational programmes can lead to improvement in the management of these patients. Since application of the results of important clinical trials and expert clinical guidelines into clinical practice leads to improved patient care and outcomes, we propose to test a quality improvement programme in a general group of hospitals in Europe

mAPN: Modeling, Analysis, and Exploration of Algorithmic and Parallelism Adaptivity

Using parallel embedded systems these days is increasing. They are getting more complex due to integrating multiple functionalities in one application or running numerous ones concurrently. This concerns a wide range of applications, including streaming applications, commonly used in embedded systems. These applications must implement adaptable and reliable algorithms to deliver the required performance under varying circumstances (e.g., running applications on the platform, input data, platform variety, etc.). Given the complexity of streaming applications, target systems, and adaptivity requirements, designing such systems with traditional programming models is daunting. This is why model-based strategies with an appropriate Model of Computation (MoC) have long been studied for embedded system design. This work provides algorithmic adaptivity on top of parallelism for dynamic dataflow to express larger sets of variants. We present a multi-Alternative Process Network (mAPN), a high-level abstract representation in which several variants of the same application coexist in the same graph expressing different implementations. We introduce mAPN properties and its formalism to describe various local implementation alternatives. Furthermore, mAPNs are enriched with metadata to Provide the alternatives with quantitative annotations in terms of a specific metric. To help the user analyze the rich space of variants, we propose a methodology to extract feasible variants under user and hardware constraints. At the core of the methodology is an algorithm for computing global metrics of an execution of different alternatives from a compact mAPN specification. We validate our approach by exploring several possible variants created for the Automatic Subtitling Application (ASA) on two hardware platforms.Comment: 26 PAGES JOURNAL PAPE

Range-resolved optical interferometric signal processing

The ability to identify the range of an interferometric signal is very useful in interferometry, allowing the suppression of parasitic signal components or permitting several signal sources to be multiplexed. Two novel range-resolved optical interferometric signal processing techniques, employing very different working principles, are theoretically described and experimentally demonstrated in this thesis. The first technique is based on code-division multiplexing (CDM), which is combined with single-sideband signal processing, resulting in a technique that, unlike prior work, only uses a single, regular electro-optic phase modulator to perform both range-based signal identification and interferometric phase evaluation. The second approach uses sinusoidal optical frequency modulation (SFM), induced by injection current modulation of a diode laser, to introduce range-dependent carriers to determine phase signals in interferometers of non-zero optical path difference. Here, a key innovation is the application of a smooth window function, which, when used together with a time-variant demodulation approach, allows optical path lengths of constituent interferometers to be continuously and independently variable, subject to a minimum separation, greatly increasing the practicality of the approach. Both techniques are applied to fibre segment interferometry, where fibre segments that act as long-gauge length interferometric sensors are formed between pairs of partial in-fibre reflectors. Using a regular single-mode laser diode, six fibre segments of length 12.5 cm are multiplexed with a quadrature bandwidth of 43 kHz and a phase noise floor of 0.19 mrad · Hz -0.5 using the SFM technique. In contrast, the 16.5 m spatial resolution achieved with the CDM technique points towards its applicability in medium-to-long range sensing. The SFM technique also allows high linearity, with cyclic errors as low as 1 mrad demonstrated, and with modelling indicating further room for improvement. Additionally, in an industrial measurement, the SFM technique is applied to single-beam, multi-surface vibrometry, allowing simultaneous differential measurements between two vibrating surfaces

Wind Turbine Controls for Farm and Offshore Operation

Development of advanced control techniques is a critical measure for reducing the cost of energy for wind power generation, in terms of both enhancing energy capture and reducing fatigue load. There are two remarkable trends for wind energy. First, more and more large wind farms are developed in order to reduce the unit-power cost in installation, operation, maintenance and transmission. Second, offshore wind energy has received significant attention when the scarcity of land resource has appeared to be a major bottleneck for next level of wind penetration, especially for Europe and Asia. This dissertation study investigates on several wind turbine control issues in the context of wind farm and offshore operation scenarios. Traditional wind farm control strategies emphasize the effect of the deficit of average wind speed, i.e. on how to guarantee the power quality from grid integration angle by the control of the electrical systems or maximize the energy capture of the whole wind farm by optimizing the setting points of rotor speed and blade pitch angle, based on the use of simple wake models, such as Jensen wake model. In this study, more complex wake models including detailed wind speed deficit distribution across the rotor plane and wake meandering are used for load reduction control of wind turbine. A periodic control scheme is adopted for individual pitch control including static wake interaction, while for the case with wake meandering considered, both a dual-mode model predictive control and a multiple model predictive control is applied to the corresponding individual pitch control problem, based on the use of the computationally efficient quadratic programming solver qpOASES. Simulation results validated the effectiveness of the proposed control schemes. Besides, as an innovative nearly model-free strategy, the nested-loop extremum seeking control (NLESC) scheme is designed to maximize energy capture of a wind farm under both steady and turbulent wind. The NLESC scheme is evaluated with a simple wind turbine array consisting of three cascaded variable-speed turbines using the SimWindFarm simulation platform. For each turbine, the torque gain is adjusted to vary/control the corresponding axial induction factor. Simulation under smooth and turbulent winds shows the effectiveness of the proposed scheme. Analysis shows that the optimal torque gain of each turbine in a cascade of turbines is invariant with wind speed if the wind direction does not change, which is supported by simulation results for smooth wind inputs. As changes of upstream turbine operation affects the downstream turbines with significant delays due to wind propagation, a cross-covariance based delay estimate is proposed as adaptive phase compensation between the dither and demodulation signals. Another subject of investigation in this research is the evaluation of an innovative scheme of actuation for stabilization of offshore floating wind turbines based on actively controlled aerodynamic vane actuators. For offshore floating wind turbines, underactuation has become a major issue and stabilization of tower/platform adds complexity to the control problem in addition to the general power/speed regulation and rotor load reduction controls. However, due to the design constraints and the significant power involved in the wind turbine structure, a unique challenge is presented to achieve low-cost, high-bandwidth and low power consumption design of actuation schemes. A recently proposed concept of vertical and horizontal vanes is evaluated to increase damping in roll motion and pitch motion, respectively. The simulation platform FAST has been modified including vertical and horizontal vane control. Simulation results validated the effectiveness of the proposed vertical and horizontal active vane actuators

Conception d'un réseau de plots configurables multifonctions analogiques et numériques combiné à un réseau de distribution de puissance intégrés à l'échelle de la tranche de silicium

RÉSUMÉ De nos jours, les systèmes électroniques sont en constante croissance en taille et en complexité. Cette complexité combinée à la réduction du temps de mise en marché rendant le design de systèmes électroniques un grand défi pour les designers. Une plateforme de prototypage a récemment été introduite afin de s’attaquer toutes ces contraintes à la fois. Cette plateforme s’appuie sur l’implémentation d’un circuit configurable à l’échelle d’une tranche de silicium complète de 200mm de diamètre. Cette surface est recouverte d’une mer de plots conducteurs configurables appelés NanoPads. Ces NanoPads sont suffisamment petits pour supporter des billes d’un diamètre de 250 μm et d’un espacement de 500 μm et sont regroupés en matrices de 4×4 pour former des Cellules, qui sont à leur tour assemblées en Réticules de 32×32. Ces Réticules sont ensuite photo-répétés sur toute la surface d’une tranche de silicium et sont interconnectés entre eux pour former le WaferIC. Cet arrangement particulier de plots conducteurs configurables permet à un usager de déposer sur la surface active du WaferIC les circuits intégrés constituant un système électronique, sans tenir en compte l’orientation spatiale de ces derniers, de créer un schéma d’interconnexions, de distribution la puissance et de débuter le prototypage du système en question. Une version préliminaire a été fabriquées et testées avec succès et permet d’alimenter des circuits -intégrés et de configurer le WaferIC pour les interconnecter. Cette thèse par articles présente une nouvelle version du WaferIC avec une nouvelle proposition de distribution de la puissance avec une approche de maîtres-esclaves qui met en valeur l’utilisation de plusieurs rails d’alimentation afin d’améliorer le rendement énergétique. Il est également mis de l’avant un réseau très dense de convertisseurs analogique-numérique (CAN) et numérique-analogique (CNA) de plus de 300k éléments, tolérant aux défectuosités et aux défauts de fabrication. Ce réseau de CAN-CNA permet d’améliorer le WaferIC avec la transmission de signaux analogiques, en plus des signaux numériques. Ce manuscrit comporte trois articles : un publié chez « Springer Science & Business Media Analog Integrated Circuits and Signal Processing », un publié chez « IEEE Transactions on Circuits and Systems I : Regular Papers » et finalement un soumis chez « IEEE Transactions on Very Large Scale Integration ».----------ABSTRACT Nowadays, electronic systems are in constant growth, size and complexity; combined with time to market it makes a challenge for electronic system designers. A prototyping platform has been recently introduced and addresses all those constraints at once. This platform is based on an active 200 mm in diameter wafer-scale circuit, which is covered with a set of small configurable and conductive pads called NanoPads. These NanoPads are designed to be small enough to support any integrated-circuit μball of a 250 μm diameter and 500 μm of pitch. They are assembled in a 4×4 matrix, forming a Unit-Cell, which are grouped in a Reticle-Image of 32×32. These Reticle-Images are photo-repeated over the entire surface of a 200 mm in diameter wafer and are interconnected together using interreticle stitching. This active wafer-scale circuit is called a WaferIC. This particular topology and distribution of NanoPads allows an electronic system designer to manually deposit any integrated-circuit (IC) on the active alignment insensitive surface of the WaferIC, to build the netlist linking all the ICs, power-up the systems and start the prototyping of the system. In this manuscript-based thesis, we present an improved version of the WaferIC with a novel approach for the power distribution network with a master-slave topology, which makes the use of embedded dual-power-rail voltage regulators in order to improve the power efficiency and decrease thermal dissipation. We also propose a default-tolerant network of analog to digital (ADC) and digital to analog (DAC) converters of more than 300k. This ADC-DAC network allows the WaferIC to not only support digital ICs but also propagate analog signals from one NanoPad to another. This thesis includes 3 papers : one submission to "Springer Science & Business Media Analog Integrated Circuits and Signal Processing", one submission to "IEEE Transactions on Circuits and Systems I : Regular Papers" and finally one submission to "IEEE Transactions on Very Large-Scale Integration". These papers propose novel architectures of dualrail voltage regulators, configurable analog buffers and configurable voltage references, which can be used as a DAC. A novel approach for a power distribution network and the integration of all the presented architectures is also proposed with the fabrication of a testchip in CMOS 0.18 μm technology, which is a small-scale version of the WaferIC