Digital Radio Encoding and Power Amplifier Design for Multimode and Multiband Wireless Communications

The evolution of wireless technology has necessitated the support of multiple communication standards by mobile devices. At present, multiple chipsets/radios operating at predefined sets of modulation schemes, frequency bands, bandwidths and output power levels are used to achieve this objective. This leads to higher component counts, increased cost and limits the capacity to cope with future communication standards. In order to tackle different wireless standards using a single chipset, digital circuits have been increasingly deployed in radios and demonstrated re-configurability in different modulation schemes (multimode) and frequency bands (multiband). Despite efforts and progress made in digitizing the entire radio, the power amplifier (PA) is still designed using an conventional approach and has become the bottleneck in digital transmitters, in terms of low average power efficiency, poor compatibility with modern CMOS technology and limited re-configurability. This research addresses these issues from two aspects. The first half of the thesis investigates signal encoding issues between the modulator and PA. We propose, analyze and evaluate a new hybrid amplitude/time signal encoding scheme that significantly improves the coding efficiency and dynamic range of a digitally modulated power amplifier (DMPA) without significantly increasing design complexity. The proposed hybrid amplitude/time encoding scheme combines both the amplitude domain and the time domain to optimally encode information. Experimental results show that hybrid amplitude/time encoding results in a 35% increase in the average coding efficiency with respect to conventional time encoding, and is only 6.7% lower than peak efficiency when applied to a Wireless Local Area Network (WLAN) signal with a peak to average power ratio equal to 9.9 dB. A new DMPA architecture, based on the proposed hybrid encoding, is also proposed. The second half of this thesis presents the design, analysis and implementation of a CMOS PA that is amenable to the proposed hybrid encoding scheme. A multi-way current mode class-D PA architecture has been proposed and realized in 130 nm CMOS technology. The designed PA has satisfied the objectives of wide bandwidth (1.5 GHz - 2.7 GHz at 1 dB output power), and high efficiency (PAE 63%) in addition to demonstrating linear responses using the proposed digital encoding. A complete digital transmitter combining the encoder and the multi-way PA was also investigated. The overall efficiency is 27% modulating 7.3 dB peak to average power ratio QAM signals

Mixed-Signal Multimode Radio Software/Hardware Development Platform

Radio frequency power amplifiers (PAs) are the most challenging part of the design of radio systems since they dictate the overall system's performance in terms of power efficiency and distortion generation. The performance is further challenged by modern modulation schemes which are characterized by highly varying signal envelopes. In order to meet the spectrum mask requirements, PAs are usually operated at high power back-off to ensure linearity, at the cost of efficiency. To tackle this issue, many efficiency enhancement techniques have been presented in the literature. In fact, these techniques do increase the PA power efficiency at back-off, however, efficiency enhancement techniques do not ensure the linearity of the PA. Furthermore, these techniques may lead to additional distortion. On the other hand, several linearization techniques have been developed to mitigate the PA nonlinearity problem and allow the PA to operate at less back-off. Digital Pre-Distortion (DPD) technique is gaining more attention, as compared to other linearization techniques, thanks to its simple concept and advancements in digital signal processors (DSP) and signal converters. DPD technique consists of introducing a nonlinear function before the PA so that the overall cascaded system behaves linearly. It was clear from the literature that this technique showed good performance. Yet, it has primarily been validated using commercial test equipment, which has good capabilities, and far from the real world environment in which this technique would be implemented. Indeed, DPDs would need to be implemented in signal processors characterised by limited resources and computational accuracy. This thesis presents an implementation of several DPD models, namely look-up table (LUT), memoryless polynomial and memory polynomial (MP), on a field programmable gate array (FPGA). A novel model reformulation made this implementation possible in fixed-point arithmetic. Measurements were collected to validate the DPD models' implementation and an improvement of the signal quality was recorded in terms of error vector magnitude (EVM) and adjacent channel leakage ratio (ACLR). As many wireless access technologies must continue to coexist, multi-standard radio systems are required to reduce the cost while maintaining the interoperability. This thesis presents a development platform for multimode radio which comprises mixed-signal modules. The platform provides the capacity for hardware and software development. In fact, the FPGA under investigation allowed for the implementation of a baseband transceiver and DPD schemes. In addition, a software tool was developed as a dashboard to control and monitor the system. The radio system in the platform was optimized through the equalization of the feedback receiver frequency response performed through a simultaneous measurement of the amplitude ripple of the transmitter and receiver. Furthermore, a phase-coherent frequency synthesizer was designed to bring more flexibility by allowing the transmitter's carrier frequency to be different from the receiver's frequency

Transmitter architectures with digital modulators, D/A converters and switching-mode power amplifiers

This thesis is composed of nine publications and an overview of the research topic, which also summarises the work. The research described in this thesis focuses on research into the digitalisation of wireless communication base station transmitters. In particular it has three foci: digital modulation, D/A conversion and switching-mode power amplification. The main interest in the implementation of these circuits is in CMOS. The work summarizes the designs of several circuit blocks of a wireless transmitter base station. In the baseband stage, a multicarrier digital modulator that combines multiple modulated signals at different carrier frequencies digitally at baseband, and a multimode digital modulator that can be operated for three different communications standards, are implemented as integrated circuits. The digital modulators include digital power ramping and power level control units for transmission bursts. The upconversion of the baseband signal is implemented using an integrated digital quadrature modulator. The work presented provides insight into the digital-to-analogue interface in the transmitters. This interface is studied both by implementing an intermediate frequency D/A converter in BiCMOS technology and bandpass Delta-Sigma modulator-based D/A conversion in CMOS technology. Finally, the last part of the work discusses switching-mode power amplifiers which are experimented with both as discrete and integrated implementations in conjunction with 1-bit Delta-Sigma modulation and pulse-width modulation as input signal generation methods.Tämä väitöskirja koostuu yhdeksästä julkaisusta ja tutkimusaiheen yhteenvedosta. Väitöskirjassa esitetty tutkimus keskittyy langattaman viestinnän tukiasemien lähettimien digitalisoinnin tutkimukseen. Yksityiskohtaisemmin tutkimusalueet ovat: digitaalinen modulaatio, D/A muunnos ja kytkinmuotoiset tehovahvistimet. Näiden elektronisten piirien toteutuksessa keskitytään CMOS teknologiaan. Työ vetää yhteen useiden langattoman viestinnän tukiasemien lähettimien piirilohkojen suunnittelun. Kantataajuusasteella toteutetaan integroituna piirinä monikantoaaltoinen digitaalinen modulaattori, joka yhdistää useita moduloituja signaaleja eri kantoaalloilla digitaalisesti ja monistandardi digitaalinen modulaatori, joka tukee kolmea eri viestintästandardia. Digitaaliset modulaattoripiirit sisältävät digitaalisen tehoramping ja tehotason säätöyksikön lähetyspurskeita varten. Kantataajuussignaalin ylössekoitus toteutetaan integroitua digitaalista kvadratuurimodulaattoria käyttäen. Esitetty työ antaa näkemystä lähettimien digitalia-analogia rajapintaan, jota tutkitaan toteuttamalla välitaajuinen D/A muunnin BiCMOS teknologialla ja päästökaistainen Delta-Sigma-modulaattoripohjainen D/A muunnin CMOS teknologialla. Lopuksi työn viimeinen osa käsittelee kytkinmuotoisia tehovahvistimia, joita tutkitaan kokeellisesti sekä erilliskompontein toteutettuina piirein että integroiduin piirein toteutettuina käyttäen sisääntulosignaalin muodostamismenetemänä yksibittistä Delta-Sigma-modulaatiota ja pulssin leveys modulaatiota.reviewe

Study of Optical OFDM System for Wireless LAN Applications

The advantages of optical fiber make it possible to extend the data rate transmission and propagation distance. Orthogonal frequency division multiplexing (OFDM) as a multicarrier technique (MC) is used in hybrid optical-wireless system designs because it has the best spectral efficiency to radio frequency (RF) interference and lower multipath distortion. In this dissertation, a study and evaluation of optical OFDM based wireless local area network (W-LAN) systems are presented. The baseband of the OFDM signal is fully transmitted and up-converted to a radio frequency signal. Also, to reduce system costs, simple base stations (BSs) are interconnected to a central office (CO) via an optical fiber. All the required operations are achieved in the CO. The directly modulated laser (DML) and continuous wave (CW) laser are used in the system simulations as optical laser sources. Identical rectangular microstrip patch antennas have been used at the transmitter and the receiver as well. The simulations were carried out for different SMF and MMF lengths, and the variable wireless distance between the transmitting and receiving antennas was in a range of 40 dB to 80 dB. The purpose of this work is to provide a framework for integrating wireless and optical technologies in one system with the presence of OFDM technology. The required microstrip patch antenna parameters for the system are analyzed and designed. The microstrip patch antenna (S-parameters) is loaded into the Optisystem communication software tool in Touchstone format. As a result, this achievement gives a greater impetus to design an integrated optical-wireless system, and simulation results validate the proposed technique. Then, the integration of the microstrip patch antenna and optical OFDM system is achieved, and the performance is intensely studied. The entire system has been presented by developing analytical models and simulations. The system performance results are obtained regarding EIRP, SNR, signal constellations and BER. The results show that this integrated optical wireless link is very robust for carrying OFDM based wireless LAN signals over an optical fiber. Moreover, using an active patch antenna in the system helps to increase the coverage service to more than 30 meters when an SMF of 80 km length is utilized

Wideband CMOS Data Converters for Linear and Efficient mmWave Transmitters

With continuously increasing demands for wireless connectivity, higher\ua0carrier frequencies and wider bandwidths are explored. To overcome a limited transmit power at these higher carrier frequencies, multiple\ua0input multiple output (MIMO) systems, with a large number of transmitters\ua0and antennas, are used to direct the transmitted power towards\ua0the user. With a large transmitter count, each individual transmitter\ua0needs to be small and allow for tight integration with digital circuits. In\ua0addition, modern communication standards require linear transmitters,\ua0making linearity an important factor in the transmitter design.In this thesis, radio frequency digital-to-analog converter (RF-DAC)-based transmitters are explored. They shift the transition from digital\ua0to analog closer to the antennas, performing both digital-to-analog\ua0conversion and up-conversion in a single block. To reduce the need for\ua0computationally costly digital predistortion (DPD), a linear and wellbehaved\ua0RF-DAC transfer characteristic is desirable. The combination\ua0of non-overlapping local oscillator (LO) signals and an expanding segmented\ua0non-linear RF-DAC scaling is evaluated as a way to linearize\ua0the transmitter. This linearization concept has been studied both for\ua0the linearization of the RF-DAC itself and for the joint linearization of\ua0the cascaded RF-DAC-based modulator and power amplifier (PA) combination.\ua0To adapt the linearization, observation receivers are needed.\ua0In these, high-speed analog-to-digital converters (ADCs) have a central\ua0role. A high-speed ADC has been designed and evaluated to understand\ua0how concepts used to increase the sample rate affect the dynamic performance

CMOS Data Converters for Closed-Loop mmWave Transmitters

With the increased amount of data consumed in mobile communication systems, new solutions for the infrastructure are needed. Massive multiple input multiple output (MIMO) is seen as a key enabler for providing this increased capacity. With the use of a large number of transmitters, the cost of each transmitter must be low. Closed-loop transmitters, featuring high-speed data converters is a promising option for achieving this reduced unit cost.In this thesis, both digital-to-analog (D/A) and analog-to-digital (A/D) converters suitable for wideband operation in millimeter wave (mmWave) massive MIMO transmitters are demonstrated. A 2 76 bit radio frequency digital-to-analog converter (RF-DAC)-based in-phase quadrature (IQ) modulator is demonstrated as a compact building block, that to a large extent realizes the transmit path in a closed-loop mmWave transmitter. The evaluation of an successive-approximation register (SAR) analog-to-digital converter (ADC) is also presented in this thesis. Methods for connecting simulated and measured performance has been studied in order to achieve a better understanding about the alternating comparator topology.These contributions show great potential for enabling closed-loop mmWave transmitters for massive MIMO transmitter realizations

TDRSS multimode transponder program. Phase 2: Equipment development

This report contains a complete description of the TDRS Multimode Transponder and its associated ground support equipment. The transponder will demonstrate candidate modulation techniques to provide the required information for the design of an eventual VHF/UHF transponder suitable for installation in a user satellite, capable of operating as part of a Tracking and Data Relay Satellite (TDRS) systems. Use of geosynchronous TDRS which can serve both low data rate users at VHF and high data rate users at other frequencies has been considered. The effects of radio frequency interference from the earth and of multipath propagation due to reflections from the earth are expected to pose problems for the TDRS system at VHF. Investigations have suggested several modulation techniques that offer promise to overcome these problems

A digital polar transmitter for multi-band OFDM Ultra-WideBand

Linear power amplifiers used to implement the Ultra-Wideband standard must be backed off from optimum power efficiency to meet the standard specifications and the power efficiency suffers. The problem of low efficiency can be mitigated by polar modulation. Digital polar architectures have been employed on numerous wireless standards like GSM, EDGE, and WLAN, where the fractional bandwidths achieved are only about 1%, and the power levels achieved are often in the vicinity of 20 dBm. Can the architecture be employed on wireless standards with low-power and high fractional bandwidth requirements and yet achieve good power efficiency? To answer these question, this thesis studies the application of a digital polar transmitter architecture with parallel amplifier stages for UWB. The concept of the digital transmitter is motivated and inspired by three factors. First, unrelenting advances in the CMOS technology in deep-submicron process and the prevalence of low-cost Digital Signal processing have resulted in the realization of higher level of integration using digitally intensive approaches. Furthermore, the architecture is an evolution of polar modulation, which is known for high power efficiency in other wireless applications. Finally, the architecture is operated as a digital-to-analog converter which circumvents the use of converters in conventional transmitters. Modeling and simulation of the system architecture is performed on the Agilent Advanced Design System Ptolemy simulation platform. First, by studying the envelope signal, we found that envelope clipping results in a reduction in the peak-to-average power ratio which in turn improves the error vector magnitude performance (figure of merit for the study). In addition, we have demonstrated that a resolution of three bits suffices for the digital polar transmitter when envelope clipping is performed. Next, this thesis covers a theoretical derivation for the estimate of the error vector magnitude based on the resolution, quantization and phase noise errors. An analysis on the process variations - which result in gain and delay mismatches - for a digital transmitter architecture with four bits ensues. The above studies allow RF designers to estimate the number of bits required and the amount of distortion that can be tolerated in the system. Next, a study on the circuit implementation was conducted. A DPA that comprises 7 parallel RF amplifiers driven by a constant RF phase-modulated signal and 7 cascode transistors (individually connected in series with the bottom amplifiers) digitally controlled by a 3-bit digitized envelope signal to reconstruct the UWB signal at the output. Through the use of NFET models from the IBM 130-nm technology, our simulation reveals that our DPA is able to achieve an EVM of - 22 dB. The DPA simulations have been performed at 3.432 GHz centre frequency with a channel bandwidth of 528 MHz, which translates to a fractional bandwidth of 15.4%. Drain efficiencies of 13.2/19.5/21.0% have been obtained while delivering -1.9/2.5/5.5 dBm of output power and consuming 5/9/17 mW of power. In addition, we performed a yield analysis on the digital polar amplifier, based on unit-weighted and binary-weighted architecture, when gain variations are introduced in all the individual stages. The dynamic element matching method is also introduced for the unit-weighted digital polar transmitter. Monte Carlo simulations reveal that when the gain of the amplifiers are allowed to vary at a mean of 1 with a standard deviation of 0.2, the binary-weighted architecture obtained a yield of 79%, while the yields of the unit-weighted architectures are in the neighbourhood of 95%. Moreover, the dynamic element matching technique demonstrates an improvement in the yield by approximately 3%. Finally, a hardware implementation for this architecture based on software-defined arbitrary waveform generators is studied. In this section, we demonstrate that the error vector magnitude results obtained with a four-stage binary-weighted digital polar transmitter under ideal combining conditions fulfill the European Computer Manufacturers Association requirements. The proposed experimental setup, believed to be the first ever attempted, confirm the feasibility of a digital polar transmitter architecture for Ultra-Wideband. In addition, we propose a number of power combining techniques suitable for the hardware implementation. Spatial power combining, in particular, shows a high potential for the digital polar transmitter architecture. The above studies demonstrate the feasibility of the digital polar architecture with good power efficiency for a wideband wireless standard with low-power and high fractional bandwidth requirements

Digital polar transmitter for multi-band OFDM ultra-wideband

Master'sMASTER OF ENGINEERIN