Secure Virtualization and Multicore Platforms State-of-the-Art report

SVaM

Lattice QCD on PCs?

Current PC processors are equipped with vector processing units and have other advanced features that can be used to accelerate lattice QCD programs. Clusters of PCs with a high-bandwidth network thus become powerful and cost-effective machines for numerical simulations.Comment: Lattice2001(plenary), LaTeX source, 8 pages, figures include

Clustering Techniques : A solution for e-business

The purpose of this thesis was to provide the best clustering solution for the Archipelago web site project which would have been part of the Central Baltic Intereg IV programme 2007-2013. The entire program is a merger between the central Baltic regions of Finland, including the Åland Islands, Sweden and Estonia. A literature review of articles and research on various clustering techniques for the different sections of the project led to the findings of this document. Clustering was needed for web servers and the underlying database implementation. Additionally, the operating system used for all servers in both sections was required to present the best clustering solution. Implementing OSI layer 7 clustering for the web server cluster, MySQL database clustering and using Linux operating system would have provided the best solution for the Archipelago website. This implementation would have provided unlimited scalability, availability and high performance for the web site. Also, it is the most cost effective solution because it would utilize the commodity hardware

SIMD-Swift: Improving Performance of Swift Fault Detection

The general tendency in modern hardware is an increase in fault rates, which is caused by the decreased operation voltages and feature sizes. Previously, the issue of hardware faults was mainly approached only in high-availability enterprise servers and in safety-critical applications, such as transport or aerospace domains. These fields generally have very tight requirements, but also higher budgets. However, as fault rates are increasing, fault tolerance solutions are starting to be also required in applications that have much smaller profit margins. This brings to the front the idea of software-implemented hardware fault tolerance, that is, the ability to detect and tolerate hardware faults using software-based techniques in commodity CPUs, which allows to get resilience almost for free. Current solutions, however, are lacking in performance, even though they show quite good fault tolerance results. This thesis explores the idea of using the Single Instruction Multiple Data (SIMD) technology for executing all program\'s operations on two copies of the same data. This idea is based on the observation that SIMD is ubiquitous in modern CPUs and is usually an underutilized resource. It allows us to detect bit-flips in hardware by a simple comparison of two copies under the assumption that only one copy is affected by a fault. We implemented this idea as a source-to-source compiler which performs hardening of a program on the source code level. The evaluation of our several implementations shows that it is beneficial to use it for applications that are dominated by arithmetic or logical operations, but those that have more control-flow or memory operations are actually performing better with the regular instruction replication. For example, we managed to get only 15% performance overhead on Fast Fourier Transformation benchmark, which is dominated by arithmetic instructions, but memory-access-dominated Dijkstra algorithm has shown a high overhead of 200%

Efficient protection of the pipeline core for safety-critical processor-based systems

The increasing number of safety-critical commercial applications has generated a need for components with high levels of reliability. As CMOS process sizes continue to shrink, the reliability of ICs is negatively affected since they become more sensitive to transient faults. New circuit designs must take this fact into consideration, and incorporate adequate protection against the effects of transient faults. This paper presents a novel method for protecting the pipelined execution unit of an embedded processor. It is based on a self-configured architecture with hybrid redundancy that can mask single and multiple errors, which can occur on storage elements due to transient or permanent faults. This concept can be easily applied to any processing architecture of this nature with a high safety integrity level. Results from error-injection experiments are also reported that show that this design can maintain a non-interrupted and failure-free operation under single and double errors with a probability that exceeds 99.4%

Acceleration management: the semiconductor industry confronts the 21st century

In the recent generations of semiconductor devices, the semiconductor industry has been accelerating towards the limits of the physical sciences. As a consequence, technology managers in that industry face seven major challenges, which will threaten progress: process, complexity, performance, power, density, productivity, and quality / reliability. We believe that confronting these challenges requires a new approach to technology management both within organizations and between organizations that form the backbone of the industry. We call this new approach Acceleration Management. Acceleration Management first requires that firms cultivate deep technical knowledge and inspire creative solutions to seemingly insoluble technical problems. The second stage of Acceleration Management requires the necessary expertise to be pooled, which often demands inter-organizational cooperation. This paper explores these managerial imperatives and analyzes how new semiconductor firms--particularly in China--have created niches in the value chain even during a tumultuous time in the industry\u27s history

Scrooge Attack: Undervolting ARM Processors for Profit

Latest ARM processors are approaching the computational power of x86 architectures while consuming much less energy. Consequently, supply follows demand with Amazon EC2, Equinix Metal and Microsoft Azure offering ARM-based instances, while Oracle Cloud Infrastructure is about to add such support. We expect this trend to continue, with an increasing number of cloud providers offering ARM-based cloud instances. ARM processors are more energy-efficient leading to substantial electricity savings for cloud providers. However, a malicious cloud provider could intentionally reduce the CPU voltage to further lower its costs. Running applications malfunction when the undervolting goes below critical thresholds. By avoiding critical voltage regions, a cloud provider can run undervolted instances in a stealthy manner. This practical experience report describes a novel attack scenario: an attack launched by the cloud provider against its users to aggressively reduce the processor voltage for saving energy to the last penny. We call it the Scrooge Attack and show how it could be executed using ARM-based computing instances. We mimic ARM-based cloud instances by deploying our own ARM-based devices using different generations of Raspberry Pi. Using realistic and synthetic workloads, we demonstrate to which degree of aggressiveness the attack is relevant. The attack is unnoticeable by our detection method up to an offset of -50mV. We show that the attack may even remain completely stealthy for certain workloads. Finally, we propose a set of client-based detection methods that can identify undervolted instances. We support experimental reproducibility and provide instructions to reproduce our results.Comment: European Commission Project: LEGaTO - Low Energy Toolset for Heterogeneous Computing (EC-H2020-780681