Simulation of FinFET Structures

The intensive downscaling of MOS transistors has been the major driving force behind the aggressive increases in transistor density and performance, leading to more chip functionality at higher speeds. While on the other side the reduction in MOSFET dimensions leads to the close proximity between source and drain, which in turn reduces the ability of the gate electrode to control the potential distribution and current flow in the channel region and also results in some undesirable effects called the short-channel effects. These limitations associated with downscaling of MOSFET device geometries have lead device designers and researchers to number of innovative techniques which include the use of different device structures, different channel materials, different gate-oxide materials, different processes such as shallow trench isolation, source/drain silicidation, lightly doped extensions etc. to enable controlled device scaling to smaller dimensions. A lot of research and development works have been done in these and related fields and more remains to be carried out in order to exploit these devices for the wider applications

Device and Circuit Level EMI Induced Vulnerability: Modeling and Experiments

Electro-magnetic interference (EMI) commonly exists in electronic equipment containing semiconductor-based integrated circuits (ICs). Metal-oxide-semiconductor field-effect-transistors (MOSFETs) in the ICs may be disrupted under EMI conditions due to transient voltage-current surges, and their internal states may change undesirably. In this work, the vulnerabilities of silicon MOSFETs under EMI are studied at the device and the circuit levels, categorized as non-permanent upsets (``Soft Errors'') and permanent damages (``Hard Failures''). The Soft Errors, such as temporary bit errors and waveform distortions, may happen or be intensified under EMI, as the transient disruptions activate unwanted and highly non-linear changes inside MOSFETs, such as Impact Ionization and Snapback. The system may be corrected from the erroneous state when the EMI condition is removed. We simulate planar silicon n-type MOSFETs at the device level to study the physical mechanisms leading to or complicate the short-term, signal-level Soft Errors. We experimentally tested commercially available MOSFET devices. Not included in regular MOSFET models, exponential-like current increases as the terminal voltage increases are observed and explained using the device-level knowledge. We develop a compact Soft Error model, compatible with circuit simulators using lumped (or compact-model) components and closed-form expressions, such as SPICE, and calibrate it with our in-house experimental data using an in-house extraction technique based on the Genetic Algorithm. Example circuits are simulated using the extracted device model and under EMI-induced transient disruptions. The EMI voltage-current disruptions may also lead to permanent Hard Failures that cannot be repaired without replacement. One type of Hard Failures, the MOSFET gate dielectric (or ``oxide'') breakdown, can result in input-output relation changes and additional thermal runaway. We have fabricated individual MOSFET devices at the FabLab at the University of Maryland NanoCenter. We experimentally stress-test the fabricated devices and observe the rapid, permanent oxide breakdown. Then, we simulate a nano-scale FinFET device with ultra-thin gate oxide at the device level. Then, we apply the knowledge from our experiments to the simulated FinFET, producing a gate oxide breakdown Hard Failure circuit model. The proposed workflow enables the evaluation of EMI-induced vulnerabilities in circuit simulations before actual fabrication and experiments, which can help the early-stage prototyping process and reduce the development time

Two dimensional quantum and reliability modelling for lightly doped nanoscale devices

The downscaling of MOSFET devices leads to well-studied short channel effects and more complex quantum mechanical effects. Both quantum and short channel effects not only alter the performance but they also affect the reliability. This continued scaling of the MOS device gate length puts a demand on the reduction of the gate oxide thickness and the substrate doping density. Quantum mechanical effects give rise to the quantization of energy in the conduction band, which consequently creates a larger effective bandgap and brings a displacement of the inversion layer charge out of the Si/SiO2 interface. Such a displacement of charge is equivalent to an increase in the effective oxide layer thickness, a growth in the threshold voltage, and a decrease in the current level. Therefore, using the classical analysis approach without including the quantum effects may lead to perceptible errors in the prognosis of the performance of modern deep submicron devices. In this work, compact Verilog-A compatible 2D models including quantum short channel effects and confinement for the potential, threshold voltage, and the carrier charge sheet density for symmetrical lightly doped double-gate MOSFETs are developed. The proposed models are not only applicable to ultra-scaled devices but they have also been derived from analytical 2D Poisson and 1D Schrodinger equations including 2D electrostatics, in order to incorporate quantum mechanical effects. Electron and hole quasi-Fermi potential effects were considered. The models were further enhanced to include negative bias temperature instability (NBTI) in order to assess the reliability of the device. NBTI effects incorporated into the models constitute interface state generation and hole-trapping. The models are continuous and have been verified by comparison with COMSOL and BALMOS numerical simulations for channel lengths down to 7nm; very good agreement within ±5% has been observed for silicon thicknesses ranging from 3nm to 20nm at 1 GHz operation after 10 years

Estudio del diseño de un circuito de voltaje de referencia para aplicaciones de bajo voltaje y bajo consumo de energía

Este trabajo de investigación describe el funcionamiento de los circuitos que permiten la generación de un voltaje de referencia estable ante variaciones en la temperatura y el voltaje de alimentación. Las topologías clásicas de circuitos de voltaje de referencia limitan el voltaje que entregan a valores cercanos a 1.2 V, impidiendo que aplicaciones de menor voltaje puedan hacer uso de dichos circuitos. El principal inconveniente yace en que las topologías clásicas de estos circuitos limitan el voltaje que entregan a valores cercanos a 1.2 V. Actualmente muchos circuitos integrados se diseñan para operar con voltajes menores a 1.2 V, de modo que es necesario plantear las consideraciones que permitan el diseño de un circuito de voltaje de referencia de bajo voltaje. El propósito de este trabajo de investigación es exponer los fundamentos para el diseño de un circuito de voltaje de referencia. Se desarrolla la teoría que permite la obtención de un voltaje independiente de la temperatura. Posteriormente se analizan dos topologías: una convencional y otra de bajo voltaje. Esta última sirve de referencia para el diseño de voltaje de referencia de bajo voltaje. En la parte final de esta investigación se enuncian conclusiones sobre el marco teórico revisado. También se mencionan recomendaciones para el diseño de un circuito de bajo voltaje.Trabajo de investigació

Oxygen-insertion Technology for CMOS Performance Enhancement

Until 2003, the semiconductor industry followed Dennard scaling rules to improve complementary metal-oxide-semiconductor (CMOS) transistor performance. However, performance gains with further reductions in transistor gate length are limited by physical effects that do not scale commensurately with device dimensions: short-channel effects (SCE) due to gate-leakage-limited gate-oxide thickness scaling, channel mobility degradation due to enhanced vertical electric fields, increased parasitic resistances due to reductions in source/drain (S/D) contact area, and increased variability in transistor performance due to random dopant fluctuation (RDF) effects and gate work function variations (WFV). These emerging scaling issues, together with increased process complexity and cost, pose severe challenges to maintaining the exponential scaling of transistor dimensions. This dissertation discusses the benefits of oxygen-insertion (OI) technology, a CMOS performance booster, for overcoming these challenges. The benefit of OI technology to mitigate the increase in sheet resistance ($R_{sh}$) with decreasing junction depth ($X_J$) for ultra-shallow-junctions (USJs) relevant for deep-sub-micron planar CMOS transistors is assessed through the fabrication of $R_{sh}$ test structures, electrical characterization, and technology computer-aided design (TCAD) simulations. Experimental and secondary ion mass spectroscopy (SIMS) analyses indicate that OI technology can facilitate low-resistivity USJ formation by reducing $R_{sh}$ and $X_J$ due to retarded transient-enhanced-diffusion (TED) effects and enhanced dopant retention during post-implantation thermal annealing. It is also shown that a low-temperature-oxide (LTO) capping can increase $R_{sh}$ unfavorably due to lower dopant activation levels, which can be alleviated by OI technology. This dissertation extends the evaluation of OI technology to advanced FinFET technology, targeting 7/8-nm low power technology node. A bulk-Si FinFET design comprising a super-steep retrograde (SSR) fin channel doping profile achievable with OI technology is studied by three-dimensional (3-D) TCAD simulations. As compared with the conventional bulk-Si (control) FinFET design with a heavily-doped fin channel doping profile, SSR FinFETs can achieve higher $I_{on}/I_{off}$ ratios and reduce the sensitivity of device performance to variations due to the lightly doped fin channel. As compared with the SOI FinFET design, SSR FinFETs can achieve similarly low $V_{DD,min}$ for 6T-SRAM cell yield estimation. Both SSR and SOI design can provide for as much as 100 mV reduction in $V_{DD,min}$ compared with the control FinFET design. Overall, the SSR FinFET design that can be achieved with OI technology is demonstrated to be a cheaper alternative to the SOI FinFET technology for extending CMOS scaling beyond the 10-nm node. Finally, this dissertation investigates the benefits of OI technology for reducing the Schottky barrier height ($\Phi_{Bp}$) of a Pt/Ti/p-type Si metal-semiconductor (M/S) contact, which can be expected to help reduce the specific contact resistivity for a p-type silicon contact. Electrical measurements of back-to-back Schottky diodes, SIMS, and X-ray photoelectron spectroscopy (XPS) show that the reduction in $\Phi_{Bp}$ is associated with enhanced Ti 2p and Si 2p core energy level shifts. OI technology is shown to favor low-$\Phi_{Bp}$ Pt monosilicide formation during forming gas anneal (FGA) by suppressing the grain boundary diffusion of Pt atoms into the crystalline Si substrate

Robust Design With Increasing Device Variability In Sub-Micron Cmos And Beyond: A Bottom-Up Framework

My Ph.D. research develops a tiered systematic framework for designing process-independent and variability-tolerant integrated circuits. This bottom-up approach starts from designing self-compensated circuits as accurate building blocks, and moves up to sub-systems with negative feedback loop and full system-level calibration. a. Design methodology for self-compensated circuits My collaborators and I proposed a novel design methodology that offers designers intuitive insights to create new topologies that are self-compensated and intrinsically process-independent without external reference. It is the first systematic approaches to create "correct-by-design" low variation circuits, and can scale beyond sub-micron CMOS nodes and extend to emerging non-silicon nano-devices. We demonstrated this methodology with an addition-based current source in both 180nm and 90nm CMOS that has 2.5x improved process variation and 6.7x improved temperature sensitivity, and a GHz ring oscillator (RO) in 90nm CMOS with 65% reduction in frequency variation and 85ppm/oC temperature sensitivity. Compared to previous designs, our RO exhibits the lowest temperature sensitivity and process variation, while consuming the least amount of power in the GHz range. Another self-compensated low noise amplifiers (LNA) we designed also exhibits 3.5x improvement in both process and temperature variation and enhanced supply voltage regulation. As part of the efforts to improve the accuracy of the building blocks, I also demonstrated experimentally that due to "diversification effect", the upper bound of circuit accuracy can be better than the minimum tolerance of on-chip devices (MOSFET, R, C, and L), which allows circuit designers to achieve better accuracy with less chip area and power consumption. b. Negative feedback loop based sub-system I explored the feasibility of using high-accuracy DC blocks as low-variation "rulers-on-chip" to regulate high-speed high-variation blocks (e.g. GHz oscillators). In this way, the trade-off between speed (which can be translated to power) and variation can be effectively de-coupled. I demonstrated this proposed structure in an integrated GHz ring oscillators that achieve 2.6% frequency accuracy and 5x improved temperature sensitivity in 90nm CMOS. c. Power-efficient system-level calibration To enable full system-level calibration and further reduce power consumption in active feedback loops, I implemented a successive-approximation-based calibration scheme in a tunable GHz VCO for low power impulse radio in 65nm CMOS. Events such as power-up and temperature drifts are monitored by the circuits and used to trigger the need-based frequency calibration. With my proposed scheme and circuitry, the calibration can be performed under 135pJ and the oscillator can operate between 0.8 and 2GHz at merely 40[MICRO SIGN]W, which is ideal for extremely power-and-cost constraint applications such as implantable biomedical device and wireless sensor networks

Study of MoS2/high-k Interface and Implementation of MoS2 Based Memristor for Neuromorphic Computing Applications

The scientific world is witnessing an unprecedented triumph of artificial neural network (ANN)- a computing system inspired by the biological neural network. With the enthralling quest for Internet of Everything (IoE), it is expected to have an unparalleled dominance of ANN in our day-to-day life. In recent times, memristor has come as an emerging candidate to realize ANN through emulating biological synapse and neuron behavior. Molybdenum disulfide (MoS2), one well-known two-dimensional (2D) transition metal dichalcogenides (TMDCs), has drawn interest for high speed, flexible, low power electronic devices since it has a tunable bandgap, reasonable carrier mobility, high Young\u27s modulus, and large surface to volume ratio. Hence, in this work, 2D MoS2 based field effect transistor (FET) and memristor devices have been developed to evaluate the performance for advanced logic and neuromorphic computing applications. We probe the superior quality of 2D/high-? dielectric interfaces by fabricating MoS2 based FET transistors with different gate dielectrics. This low interface trap density of ~7x10^10 states/cm2-eV at the MoS2/Al2O3 interface establishes the case for van der Waals systems where the superior quality of 2D/high-? dielectric interfaces can produce high performance electronic and optoelectronic devices. This work also demonstrates Au/MoS2/Ag threshold switching memristor (TSM) device with low threshold voltage, sharp switching, high ON-OFF ratio and endurance. A leaky integration-and-firing (LIF) neuron is implemented with this TSM. It successfully emulates the key characteristics of a biological neuron. The LIF neuron is monolithically integrated with the MoS2 based synapse device to realize a single layer perceptron operation and Boolean logic gates. The Au/MoS2/Ag TSM device also imitates a nociceptor, the single device exhibits all the key features of nociceptors including threshold, relaxation, no adaptation and sensitization phenomena of allodynia and hyperalgesia. This work indicates applicability of this device in artificial intelligence systems-based neuromorphic hardware applications and artificial sensory alarm system

Graphene nano-ribbon and transition metal dichalcogenide field-effect transistor modeling and circuit simulation

This dissertation presents a modeling and simulation study of graphene nano-ribbon and transition metal dichalcogenide field-effect transistors. Through compact modeling, SPICE implementation of the transistors is realized, and circuit-level simulation is enabled. Extensive simulation studies are performed to evaluate the performance of these two emerging devices

Advanced Silicon and Germanium Transistors for Future P-channel MOSFET Applications

Ph.DDOCTOR OF PHILOSOPH