Climate uniformity: its influence on team communication quality, task conflict, and team performance

We investigated whether climate uniformity (the pattern of climate perceptions of organizational support within the team) is related to task conflict, team communication quality, and team performance. We used a sample composed of 141 bank branches and collected data at three time points. The results obtained showed that, after controlling for aggregate team climate, climate strength and their interaction, a type of non-uniform climate pattern (weak dissimilarity) was directly related to task conflict and team communication quality. Teams with weak dissimilarity non-uniform patterns tended to show higher levels of task conflict and lower levels of team communication quality than teams with uniform climate patterns. The relationship between weak dissimilarity patterns and team performance was fully mediated by team communication quality

The Main and Interaction Effects of Process Rigor, Process Standardization, and Process Agility on System Performance in Distributed IS Development: An Ambidexterity Perspective

Information systems (IS) development is becoming increasingly more geographically dispersed. Although process rigor, process standardization, and process agility are generally believed to have a positive impact on software development, it has not been well understood how these process capabilities affect distributed IS development. More important, no prior research has investigated their interaction effects. Drawing upon prior literature on organizational ambidexterity, we hypothesize: positive main effects of process rigor, process standardization, and process agility; a positive interaction effect of process rigor and process agility; and a positive interaction effect of process standardization and process agility on system performance in distributed development. Our data analysis results support a positive main effect of the three process capabilities. We find a positive interaction effect of process rigor and process agility suggesting positive process ambidexterity of rigor and agility. Surprisingly, we find a negative interaction effect of process agility and process standardization suggesting negative process ambidexterity of agility and standardizatio

Fast-Gated 16 x 16 SPAD Array With 16 on-Chip 6 ps Time-to-Digital Converters for Non-Line-of-Sight Imaging

We present the design and characterization of a fully-integrated array of 16 x 16 Single-Photon Avalanche Diodes (SPADs) with fast-gating capabilities and 16 on-chip 6 ps time-to-digital converters, which has been embedded in a compact imaging module. Such sensor has been developed for Non-Line-Of-Sight imaging applications, which require: i) a narrow instrument response function, for a centimeter-accurate single-shot precision; ii) fast-gated SPADs, for time-filtering of directly reflected photons; iii) high photon detection probability, for acquiring faint signals undergoing multiple scattering events. Thanks to a novel multiple differential SPAD-SPAD sensing approach, SPAD detectors can be swiftly activated in less than 500 ps and the full-width at half maximum of the instrument response function is always less than 75 ps (60 ps on average). Temporal responses are consistently uniform throughout the gate window, showing just few picoseconds of time dispersion when 30 ns gate pulses are applied, while the differential non-linearity is as low as 250 fs. With a photon detection probability peak of 70% at 490 nm, a fill-factor of 9.6% and up to 1.6 . 10(8) photon time-tagging measurements per second, such sensor fulfills the demand for fully-integrated imaging solutions optimized for non-line-of-sight imaging applications, enabling to cut exposure times while also optimizing size, weight, power and cost, thus paving the way for further scaled architectures

In the Furtherance of Justice, Injustice, or Both? A Multilevel Analysis of Courtroom Context and the Implementation of Three Strikes

A hierarchical logistic model is used to analyze data on Three Strikes-eligible offenders in California and the counties in which they are sentenced. The analysis finds that discretion is widely exercised by elected prosecutors and judges in the administration of Three Strikes. Discretion functions as a “safety valve” and preserves some sentencing proportionality, but may also allow political concerns to influence sentencing decisions. A more conservative political environment is strongly associated with stricter application of the law. Consistent with racial threat theory, eligible felons are more likely to receive Three Strikes sentences in counties with larger Latino populations. However, the size of the black population has no significant effect. Higher unemployment rates are associated with more stringent application of the law. Prosecutorial and judicial discretion benefits offenders unequally. Controlling for legally relevant factors, black offenders are more likely to receive Three Strikes sentences, while younger ones are less likely

Modeling of pattern dependencies in the fabrication of multilevel copper metallization

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2007.Includes bibliographical references (p. 295-303).Multilevel copper metallization for Ultra-Large-Scale-Integrated (ULSI) circuits is a critical technology needed to meet performance requirements for advanced interconnect technologies with sub-micron dimensions. It is well known that multilevel topography resulting from pattern dependencies in various processes, especially copper Electrochemical Deposition (ECD) and Chemical-Mechanical Planarization (CMP), is a major problem in interconnects. An integrated pattern dependent chip-scale model for multilevel copper metallization is contributed to help understand and meet dishing and erosion requirements, to optimize the combined plating and polishing process to achieve minimal environmental impact, higher yield and performance, and to enable optimization of layout and dummy fill designs. First, a physics-based chip-scale copper ECD model is developed. By considering copper ion depletion effects, and surface additive adsorption and desorption, the plating model is able to predict the initial topography for subsequent CMP modeling with sufficient accuracy and computational efficiency. Second, a compatible chip-scale CMP modeling is developed.(cont.) The CMP model integrates contact wear and density-step-height approaches, so that a consistent and coherent chip-scale model framework can be used for copper bulk polishing, copper over-polishing, and barrier layer polishing stages. A variant of this CMP model is developed which explicitly considers the pad topography properties. Finally, ECD and CMP parts are combined into an integrated model applicable to single level and multilevel metallization cases. The integrated multilevel copper metallization model is applied to the co-optimization of the plating and CMP processes. An alternative in-pattern (rather than between-pattern) dummy fill strategy is proposed. The integrated ECD/CMP model is applied to the optimization of the in-pattern fill, to achieve improved ECD uniformity and final post-CMP topography.by Hong Cai.Ph.D

Advanced analog layout design automation in compliance with density uniformity

To fabricate a reliable integrated circuit chip, foundries follow specific design rules and layout processing techniques. One of the parameters, which affect circuit performance and final electronic product quality, is the variation of thickness for each semiconductor layer within the fabricated chips. The thickness is closely dependent on the density of geometric features on that layer. Therefore, to ensure consistent thickness, foundries normally have to seriously control distribution of the feature density on each layer by using post-processing operations. In this research, the methods of controlling feature density distribution on different layers of an analog layout during the process of layout migration from an old technology to a new one or updated design specifications in the same technology have been investigated. We aim to achieve density-uniformity-aware layout retargeting for facilitating manufacturing process in the advanced technologies. This can offer an advantage right to the design stage for the designers to evaluate the effects of applying density uniformity to their drafted layouts, which are otherwise usually done by the foundries at the final manufacturing stage without considering circuit performance. Layout modification for density uniformity includes component position change and size modification, which may induce crosstalk noise caused by extra parasitic capacitance. To effectively control this effect, we have also investigated and proposed a simple yet accurate analytic method to model the parasitic capacitance on multi-layer VLSI chips. Supported by this capacitance modeling research, a unique methodology to deal with density-uniformity-aware analog layout retargeting with the capability of parasitic capacitance control has been presented. The proposed operations include layout geometry position rearrangement, interconnect size modification, and extra dummy fill insertion for enhancing layout density uniformity. All of these operations are holistically coordinated by a linear programming optimization scheme. The experimental results demonstrate the efficacy of the proposed methodology compared to the popular digital solutions in terms of minimum density variation and acute parasitic capacitance control